Chip interconnect and packaging deposition methods and structures

• US 7,147,766 B2
• Filed: 04/04/2003
• Issued: 12/12/2006
• Est. Priority Date: 09/17/1999
• Status: Expired due to Term

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: ASM NuTool, Inc. (ASM International NV)
• Inventors: Talieh, Homayoun, Basol, Bulent, Uzoh, Cyprian Emeka
• Primary Examiner(s): Wong, Edna
• Application Number:
  US10/407,892
• Publication Number:
  US 20030164302A1
• Time in Patent Office: 1,348 Days
• Field of Search: 205/118, 205/123, 205/221, 205/222
• US Class Current: 205/118
• CPC Class Codes: C23C 18/1608 from pretreatment step, i.e. selective pre-treatment
• CPC Class Codes: C23C 18/165 Multilayered product layered product B32B
• CPC Class Codes: C23C 18/1651 Two or more layers only obtained by electroless plating
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/1696 Control of atmosphere
• CPC Class Codes: C23C 18/1848 by electrochemical pretreatment
• CPC Class Codes: C23C 18/31 Coating with metals
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 5/10 Electroplating with more than one layer of the same or of different metals for bearings C25D7/10
• CPC Class Codes: C25D 5/22 Electroplating combined with mechanical treatment during the deposition
• CPC Class Codes: C25D 5/34 Pretreatment of metallic surfaces to be electroplated
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 : By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1089 : Stacks of seed layers
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

Claims

1. A method of electroplating a metal in a feature formed in a substrate, the substrate having a top surface, the feature having a bottom and sidewalls, the method comprising:

depositing a barrier layer on the top surface of the substrate and the bottom and sidewalls of the feature;

depositing a seed layer of the metal on the barrier layer;

removing the seed layer from the top surface of the substrate, thereby exposing the barrier layer on the top surface of the substrate and leaving the seed layer on the sidewalls and on the bottom of the feature;

during the removing, applying an electrical potential between the substrate and an electrode; and

electroplating the metal on the seed layer so that the metal fills the feature with substantially no electroplating on the top surface.

2. A method of electroplating a metal according to claim 1, wherein the removing comprises chemical mechanical polishing.

3. A method of electroplating a metal according to claim 2, wherein the metal comprises copper.

4. A method of electroplating a metal according to claim 3, wherein the barrier layer comprises tantalum and tantalum nitride.

5. A method of electroplating a metal according to claim 1, wherein the metal comprises copper.

6. A method of electroplating a metal according to claim 5, wherein the barrier layer comprises tantalum and tantalum nitride.

7. A method of electroplating a metal according to claim 1, wherein the barrier layer comprises tantalum and tantalum nitride.

8. A method of electroplating a metal according to claim 1, wherein the electroplating the metal fills the feature to an excess, the method further comprising removing the excess metal so that a top surface of the metal is substantially planar with the barrier layer on the top surface of the substrate.

9. A method of electroplating a metal according to claim 1, further comprising removing the barrier layer from the top surface of the substrate.

10. A method of electroplating a metal according to claim 1, wherein the electrode comprises an anode and the substrate comprises a cathode.

11. A method of electroplating a metal according to claim 1, wherein the electrode comprises a cathode and the substrate comprises an anode.

12. A method of electroplating a metal according to claim 1, wherein the electrode comprises a cathode and the seed layer on the top surface of the substrate comprises an anode.

13. A method of electroplating a metal according to claim 1, wherein removing the seed layer comprises polishing the seed layer on the top surface of the substrate with a pad.

14. A method of electroplating a metal according to claim 1, wherein electroplating the metal comprises polishing the top surface of the substrate with a pad.

15. A method of electroplating a metal according to claim 1, wherein the removing the seed layer and the electroplating the metal occur simultaneously.

16. A method of electroplating a metal on a substrate including a feature having a bottom and sidewalls, the substrate having a barrier layer and a seed layer deposited on a top surface of the substrate and on the bottom and the sidewalls of the feature, the method comprising:

removing the seed layer from the top surface of the substrate, thereby exposing the barrier layer on the top surface of the substrate and leaving the seed layer on the sidewalls and on the bottom of the feature;

during the removing, applying an electrical potential between the substrate and an electrode; and

electroplating the metal on the seed layer so that the metal fills the feature, with substantially no electroplating on the top surface.

17. A method of electroplating a metal according to claim 16, wherein the removing comprises chemical mechanical polishing.

18. A method of electroplating a metal according to claim 17, wherein the metal comprises copper.

19. A method of electroplating a metal according to claim 18, wherein the barrier layer comprises tantalum and tantalum nitride.

20. A method of electroplating a metal according to claim 16, wherein the metal comprises copper.

21. A method of electroplating a metal according to claim 20, wherein the barrier layer comprises tantalum and tantalum nitride.

22. A method of electroplating a metal according to claim 16, wherein the barrier layer comprises tantalum and tantalum nitride.

23. A method of electroplating a metal according to claim 16, wherein the electroplating the metal fills the feature to an excess, the method further comprising removing the excess metal so that a top surface of the metal is substantially planar with the barrier layer on the top surface of the substrate.

24. A method of electroplating a metal according to claim 16, further comprising removing the barrier layer from the top surface of the substrate.

25. A method of electroplating a metal according to claim 16, wherein the electrode comprises an anode and the substrate comprises a cathode.

26. A method of electroplating a metal according to claim 16, wherein the electrode comprises a cathode and the substrate comprises an anode.

27. A method of electroplating a metal according to claim 16, wherein the electrode comprises a cathode and the seed layer on the top surface of the substrate comprises an anode.

28. A method of electroplating a metal according to claim 16, wherein removing the seed layer comprises polishing the seed layer on the top surface of the substrate with a pad.

29. A method of electroplating a metal according to claim 16, wherein electroplating the metal comprises polishing the top surface of the substrate with a pad.

30. A method of electroplating a metal according to claim 16, wherein the removing the seed layer and the electroplating the metal occur simultaneously.