Vertical semiconductor devices or chips and method of mass production of the same

• US 7,148,075 B2
• Filed: 06/05/2004
• Issued: 12/12/2006
• Est. Priority Date: 06/05/2004
• Status: Expired due to Fees

• Current Assignee: Hui Peng, Wei Luo
• Original Assignee: Hui Peng, Wei Luo
• Inventors: Luo, Wei, Peng, Hui
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US10/862,086
• Publication Number:
  US 20050269575A1
• Time in Patent Office: 920 Days
• Field of Search: 438/22, 438/37, 438/46, 438/47, 438/455, 438/459, 438/464
• US Class Current: 438/22
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/405 Reflective materials

Abstract

The vertical semiconductor chips or devices have all of advantages of flip chip technique and without its disadvantages. The present invention discloses methods of mass production of the vertical semiconductor chips or devices comprising GaN, GaInP, and GaInNP based LEDs with higher crystal quality, higher throughput, higher yield, and lower cost. The methods comprise the following process steps in the order presented: growing a first-type cladding layer, disposing a reflector/Ohmic layer, disposing a second intermediate layer, disposing an electrically conductive supporting plate, removing the original substrate and the first-type cladding layer exposed, growing an epitaxial layer comprising an active layer and a second-type cladding layer, disposing a second-electrode, and dicing into individual dies.

Claims

1. A method for manufacturing vertical semiconductor chips or devices, comprises process steps, in the order presented:

providing a substrate;

growing a first-type cladding layer on said substrate;

disposing a second intermediate layer on said first-type cladding layer;

disposing an electrically conductive supporting plate on said second intermediate layer to form a bonded wafer;

removing said substrate from said bonded wafer so that said first-type cladding layer exposed;

growing an epitaxial layer on said first-type cladding layer;

wherein said epitaxial layer comprising an active layer which emits light and a second-type cladding layer;

disposing a patterned second-electrode on said second-type cladding layer, wherein said patterned second-electrode comprising at least one wire bonding pad.

2. The method for manufacturing vertical semiconductor chips or devices of claim 1, further comprises process steps:

(1) disposing a first intermediate layer on said substrate and growing said first-type cladding layer on said first intermediate layer; and

(2) removing said first intermediate layer after said process step of removing said substrate so that said first-type cladding layer exposed.

3. The method for manufacturing vertical semiconductor chips or devices of claim 2, wherein said first intermediate layer is selected from a group comprising:

(1) a metal layer;

(2) one or plurality of buffer layers selected from a group comprising AlN, GaN, InN, AlGaN, AlInN, and GaInN; and

(3) their combinations.

4. The method for manufacturing vertical semiconductor chips or devices of claim 3, wherein said metal layer comprises:

(1) a low melting point metal layer having melting point lower than the temperature of growing said epitaxial layer and being selected from a group comprising Cd, Sn, and In (indium);

(2) a high melting point metal layer having melting point higher than the temperature of growing said epitaxial layer and being selected from a group comprising Au and Ti; and

(3) their combinations.

5. The method for manufacturing vertical semiconductor chips or devices of claim 3, wherein a method of removing said substrate is selected from a group comprising:

(1) etching;

(2) precisely lapping/polishing;

(3) heating up said bonded wafer until said metal layer dissolved and separating said substrate from said bonded wafer; and

(4) their combinations;

wherein a method of removing said first intermediate layer being selected from a group comprising;

(1) precisely lapping/polishing;

(2) etching; and

(3) their combinations.

6. The method for manufacturing vertical semiconductor chips or devices of claim 1, further comprises a process step of disposing a reflector/Ohmic layer on said first-type cladding layer before said process step of disposing said second intermediate layer.

7. The method for manufacturing vertical semiconductor chips or devices of claim 1, further comprises a process step of texturing the top surface of said first-type cladding layer after said process step of growing a first-type cladding layer.

8. The method for manufacturing vertical semiconductor chips or devices of claim 7, further comprises a process step of disposing a reflector/Ohmic layer on said textured top surface of said first-type cladding layer before said process step of disposing said second intermediate layer.

9. The method for manufacturing vertical semiconductor chips or devices of claim 1, wherein a method for disposing said electrically conductive supporting plate is selected from a group comprising:

(1) wafer bonding;

(2) electroplating or electro-less plating;

(3) vacuum evaporation (electron beam and sputter); and

(4) their combinations.

10. The method for manufacturing vertical semiconductor chips or devices of claim 1, further comprises a process step of growing a first-type cladding thin film on said first-type cladding layer before said process step of growing said epitaxial layer on said first-type cladding layer for improving crystal quality of said epitaxial layer.

11. The method for manufacturing vertical semiconductor chips or devices of claim 1, further comprises a process step of disposing a current spreading layer between said second-type cladding layer and said patterned second-electrode.