Memory structure and method making

• US 7,148,088 B2
• Filed: 01/23/2004
• Issued: 12/12/2006
• Est. Priority Date: 01/16/2002
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Fricke, Peter, Van Brocklin, Andrew L
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Dolan, Jennifer M.
• Application Number:
  US10/764,009
• Publication Number:
  US 20040151016A1
• Time in Patent Office: 1,054 Days
• Field of Search: 438/131, 438/132, 438/467, 438/598, 438/600, 257/50, 257/209, 257/529, 257/530
• US Class Current: 438/131
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A memory structure has a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections. Each intersection includes an electrically linear resistive element in series with a voltage breakdown element.

Claims

1. A method comprising forming a plurality of row conductors to intersect with a plurality of column conductors at a plurality of intersections, each said intersection including an electrically linear resistive element in series with an unpatterned voltage breakdown element.

2. The method as defined in claim 1, wherein the forming a plurality of row conductors to intersect with a plurality of column conductors comprises:

depositing a first layer of column material;

patterning the first layer of column material to form the plurality of column conductors;

forming a voltage breakdown material on the plurality of column conductors;

forming an electrically linear resistive material upon the voltage breakdown material;

patterning the electrically linear resistive material;

depositing a layer of row material upon the patterned electrically linear resistive material;

patterning the layer of row material to form the plurality of row conductors.

3. The method as defined in claim 2, further comprising forming an electrical insulator upon the voltage breakdown material and the patterned electrically linear resistive material.

4. The method as defined in claim 2, wherein each said intersection has an unpatterned layer of material selected from the group consisting of the electrical insulator and the voltage breakdown material.

5. The method as defined in claim 2, wherein:

the electrically linear resistive material is selected from the group consisting of lightly doped microcrystalline silicon, lightly doped amorphous silicon, intrinsic silicon, refractory metal silicide nitride; and

the voltage breakdown material comprises an antifuse having a dielectric with a thickness not greater than 200 Angstroms.

6. The method as defined in claim 1, wherein the forming a plurality of row conductors to intersect with a plurality of column conductors comprises:

forming a first electrical insulator;

depositing a first layer of column material over the first electrical insulator;

patterning the first layer of column material to form the plurality of column conductors;

forming a first voltage breakdown material on the plurality of column conductors;

forming a first electrically linear resistive material upon the first voltage breakdown material;

depositing a first layer of row material upon the first electrically linear resistive material; and

patterning the first layer of row material to form a first plurality of row conductors;

forming a second electrical insulator upon the first plurality of row conductors;

depositing a second layer of column material over the second electrical insulator;

patterning the second layer of column material to form a second plurality of column conductors;

forming a second voltage breakdown material on the second plurality of column conductors;

forming a second electrically linear resistive material upon the second voltage breakdown material;

depositing a second layer of row material upon the second electrically linear resistive material; and

patterning the second layer of row material to form a second plurality of row conductors.

7. The method as defined in claim 6, wherein:

at least one of the first and second electrical insulators is unpatterned;

at least one of the first and second voltage breakdown materials is unpatterned; and

at least one of the first and second electrically linear resistive materials is patterned.

8. The method as defined in claim 6, wherein each said intersection has an unpatterned layer of material selected from the group consisting of the first and second electrical insulator and the first and second voltage breakdown materials.

9. The method as defined in claim 6, wherein:

the first and second electrically linear resistive materials are selected from the group consisting of lightly doped microcrystalline silicon, lightly doped amorphous silicon, intrinsic silicon, refractory metal silicide nitride; and

the first and second voltage breakdown materials comprise an antifuse having a dielectric with a thickness not greater than 200 Angstroms.

10. The method as defined in claim 1, wherein the forming a plurality of row conductors to intersect with a plurality of column conductors comprises:

depositing a first layer of row material;

patterning the first layer of row material to form the plurality of row conductors;

forming a first voltage breakdown material on the plurality of row conductors;

forming a first electrically linear resistive material upon the first voltage breakdown material;

depositing a layer of column material upon the first electrically linear resistive material;

patterning the layer of column material to form the plurality of column conductors;

forming a second voltage breakdown material on the plurality of column conductors;

forming a second electrically linear resistive material upon the second voltage breakdown material;

depositing a second layer of row material upon the second electrically linear resistive material; and

patterning the second layer of row material to form another plurality of said row conductors.

11. The method as defined in claim 10, wherein:

the first voltage breakdown material, upon which the first electrically linear resistive material is formed, is unpatterned;

the first electrically linear resistive material, upon which the first layer of column material is deposited, is patterned;

the second voltage breakdown material, upon which the second electrically linear resistive material is formed, is unpatterned;

the second electrically linear resistive material, upon which the second layer of row material is deposited, is patterned.

12. The method as defined in claim 10, wherein each said intersection has an unpatterned layer of material selected from the group consisting of the first voltage breakdown material and the second voltage breakdown material.

13. The method as defined in claim 10, wherein:

the first and second electrically linear resistive materials are selected from the group consisting of lightly doped microcrystalline silicon, lightly doped amorphous silicon, intrinsic silicon, refractory metal silicide nitride; and

the first and second voltage breakdown materials comprise an antifuse having a dielectric with a thickness not greater than 200 Angstroms.

14. A memory structure made by the method of claim 1.

15. The memory structure as defined in claim 14, further comprising a primary of memory elements, wherein each one said row conductor connected to one said column conductor by one said electrically linear resistive element in series with one said voltage breakdown element.

16. The memory structure as defined in claim 15, wherein each said memory element is in a memory device selected from the group consisting of a WORM memory device and a one time programmable memory device.

17. The memory structure as defined in claim 15, wherein the memory device is included in a memory apparatus that is selected from the group consisting of a digital film and a memory card.