Reducing the dielectric constant of a portion of a gate dielectric

• US 7,148,099 B2
• Filed: 06/24/2004
• Issued: 12/12/2006
• Est. Priority Date: 06/24/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doczy, Mark L., Kavalieros, Jack, Brask, Justin K., Metz, Matthew V., Datta, Suman
• Primary Examiner(s): Pham, Thanhha S.
• Application Number:
  US10/877,836
• Publication Number:
  US 20050285213A1
• Time in Patent Office: 901 Days
• Field of Search: 438/199, 438/201, 438/209, 438/211, 438/216, 438/287, 438302-303, 438/585, 438/592, 438593-594
• US Class Current: 438/216
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not

Abstract

In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.

Claims

1. A method comprising:

reducing a dielectric constant of only a vertical portion of a metal oxide gate dielectric having a horizontal portion and the vertical portion, said horizontal portion contacting a semiconductor substrate.

2. The method of claim 1 including forming said metal oxide gate dielectric in a cup-shape, said metal oxide gate dielectric having the horizontal portion and the vertical portion.

3. The method of claim 1 including maintaining a dielectric constant of the horizontal portion of said metal oxide gate dielectric.

4. The method of claim 3 including implanting said vertical portion to reduce the dielectric constant of said vertical portion of said metal oxide gate dielectric.

5. The method of claim 4 including implanting said vertical portion using an implantation angle of less than 60 degrees.

6. The method of claim 5 including implanting said vertical portion with silicon.

7. A method comprising:

forming a polysilicon gate electrode over a gate dielectric;

forming a sidewall spacer on said polysilicon gate electrode;

removing said gate dielectric and polysilicon gate electrode;

forming a metal oxide gate dielectric on said sidewall spacer, said metal oxide gate dielectric having a horizontal portion and a vertical portion, said vertical portion contacting said sidewall spacer;

forming a metal gate electrode over said metal oxide gate dielectric; and

reducing a dielectric constant of the vertical portion of said metal oxide gate dielectric.

8. The method of claim 7 wherein forming said metal oxide gate dielectric includes forming a cup-shaped metal oxide gate dielectric having the horizontal portion and the vertical portion.

9. The method of claim 8 including maintaining a dielectric constant of the horizontal portion of said metal oxide gate dielectric.

10. The method of claim 9 including using ion implantation to reduce the dielectric constant of said vertical portion.

11. The method of claim 7 wherein reducing includes forming a ternary silicate in said vertical portion.

12. The method of claim 11 including using silicon ion implantation to reduce the dielectric constant of said vertical portion.

13. The method of claim 12 including using an implant angle of less than 60 degrees to reduce the dielectric constant of said vertical portion.