Semiconductor device and fabricating method thereof

• US 7,148,113 B2
• Filed: 07/19/2005
• Issued: 12/12/2006
• Est. Priority Date: 08/25/2003
• Status: Active Grant

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: Wang, Yu-Piao
• Primary Examiner(s): Kebede, Brook
• Assistant Examiner(s): Parker, John M.
• Application Number:
  US11/160,983
• Publication Number:
  US 20050272256A1
• Time in Patent Office: 511 Days
• Field of Search: 438/275, 438/303, 438/595, 438/FOR.199, 257/E21.626, 257/E21.64, 257/E21.659
• US Class Current: 438/275
• CPC Class Codes: H01L 21/28044 the conductor comprising at least another non-silicon conductive layer
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the substrate covering a portion of the gate structures. Removing the cap layer and spacers that are not covered by the mask layer. After the mask layer is removed, a dielectric layer is formed over the substrate covering the gate structures. A self-aligned contact hole is formed in the dielectric layer. A conductive layer is formed in the self-aligned contact hole and on the dielectric layer. Since the cap layer and spacers that are not covered by the mask layer are removed and substituted by the dielectric layer having lower dielectric constant property, the parasitic capacitance can be reduced.

Claims

1. A fabrication method for a semiconductor device, comprising:

forming a gate dielectric layer on a substrate;

forming a plurality of gate structures on the substrate, wherein each gate structure is separated by a first dielectric layer, and comprises a gate conductive layer, a cap layer and a spacer;

forming a mask layer on the substrate to cover some of the gate structures;

removing the cap layer and the spacer of the gate structures that are not covered by the mask layer, wherein a gap is formed between the gate and the first dielectric layer;

removing the mask layer; and

depositing a second dielectric layer on the substrate to cover the gate structures, thereby forming voids in the second dielectric layer and in the gap.

2. The method of claim 1, wherein the mask layer is formed to cover the gate structures where a self-aligned contact is subsequently formed or the gate structures on the active region.

3. The method of claim 2, wherein the mask layer is formed to cover a part of the gate structures.

4. The method of claim 1, wherein the step of removing of the cap layer and the spacer further comprises concurrently removing the cap layer of the gate structures at a predetermined site for a gate contact.

5. The method of claim 1, wherein after the step of removing the mask layer, the method further comprises a metal silicide fabrication process to form a metal suicide layer on an exposed sidewall of the gate conductive layer.

6. The method of claim 1, wherein a dielectric constant of the second dielectric layer is lower than a dielectric constant of the cap layer and the spacer.

7. The method of claim 1, wherein an etching selectivity ratio of the cap layer and the spacer to the gate dielectric layer and the gate conductive layer is greater than 10.

8. The method of claim 1, wherein after the step of forming the second dielectric layer, the method further comprises forming a self-aligned contact in the first dielectric layer and the second dielectric layer and forming a conductive line on the second dielectric layer to electrically connect with the self-aligned contact.

9. A fabrication method for a semiconductor device, comprising:

forming a gate dielectric layer on a substrate;

forming a plurality of gate structures on the substrate, wherein each gate structure comprises a gate conductive layer, a cap layer and a spacer;

filling a first dielectric layer in between the gate structures;

forming a self-aligned contact in the first dielectric layer in between two of the gate structures;

removing the cap layer and the spacer of the gate structures to form a gap at a sidewall of the gate structures; and

forming a second dielectric layer on the first dielectric layer, thereby forming voids in the second dielectric layer and in the gap.

10. The method of claim 9, wherein the step of removing the cap layer further comprises concurrently removing the cap layer of the gate structures at a predetermined site for forming a gate contact.

11. The method of claim 9, wherein a dielectric constant of the second dielectric layer is lower than a dielectric constant of the cap layer and the spacer.

12. The method of claim 9, wherein an etching selectivity ratio of the cap layer and the spacer to the gate dielectric layer and the gate conductive layer is greater than 10.

13. The method of claim 9, wherein after the step of forming the second dielectric layer, the method further comprises forming a conductive line on the second dielectric layer to electrically connect with the self-aligned contact.