Semiconductor device with inductive component and method of making

• US 7,148,553 B1
• Filed: 08/01/2001
• Issued: 12/12/2006
• Est. Priority Date: 08/01/2001
• Status: Expired due to Fees

• Current Assignee: David Richard Stanowski
• Original Assignee: Robert B Davies
• Inventors: Davies, Robert B.
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US09/920,222
• Time in Patent Office: 1,959 Days
• Field of Search: 257/277, 257/531, 257/528, 257/516, 257/379
• US Class Current: 257/531
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top surface (49) of the inductor is substantially coplanar with an interconnect surface (31) of the semiconductor substrate, which facilitates connecting to the inductor with standard integrated circuit metallization (57).

Claims

1. An integrated circuit, comprising:

a low resistivity semiconductor substrate having a dielectric region formed therein, a trench defined in the dielectric region and including dielectric sidewalls, and an adjacent cavity defined at least partially by the substrate;

an electroplated conductive material disposed within the trench to produce an inductance having sides and a bottom, the sides of the inductance being bounded by the dielectric sidewalls and the cavity being adjacent the bottom; and

a bottom surface of the semiconductor substrate defining a first recessed region underlying the dielectric region.

2. The integrated circuit of claim 1, wherein the dielectric region includes a cap layer formed at a top surface of the semiconductor substrate and the cavity extends from the cap layer to a bottom surface of the dielectric region.

3. The integrated circuit of claim 1, wherein the conductive material includes copper.

4. The integrated circuit of claim 1, wherein the conductive material is disposed within the trench to a depth of at least five micrometers.

5. The integrated circuit of claim 1, wherein the dielectric region is formed with a silicon based dielectric.

6. The integrated circuit of claim 1, wherein the dielectric region is formed at a top surface of the semiconductor substrate, further comprising an active device formed at the top surface.

7. An integrated circuit comprising:

a low resistivity, semiconductor substrate including an active region and a dielectric region;

at least one active component positioned in the active region;

a trench formed in the dielectric region and including side-walls defined by low dielectric constant material;

high conductivity electroplated material in the trench and defining at least a portion of a passive electronic component; and

wherein the low dielectric constant material includes dielectric material defining an array of cavities therein, the dielectric material having a first dielectric constant and the cavities providing a second dielectric constant lower than the first dielectric constant to form an effective dielectric constant lower than the first dielectric constant.

8. An integrated circuit as claimed in claim 7 wherein the high conductivity electroplated material includes copper.

9. An integrated circuit as claimed in claim 7 wherein the trench is elongated and formed in the shape of an inductance.

10. An integrated circuit comprising:

a low resistivity, semiconductor substrate including an active region and a dielectric region;

at least one active component positioned in the active region;

a trench formed in the dielectric region and including side-walls defined by low dielectric constant material;

high conductivity electroplated material in the trench and defining at least a portion of a passive electronic component; and

wherein the low dielectric constant material includes dielectric material defining an array of cavities therein, the dielectric material having a first dielectric constant and the cavities providing a second dielectric constant lower than the first dielectric constant to form an effective dielectric constant lower than the first dielectric constant, wherein the dielectric material and the array of cavities produce an effective dielectric constant at least ten percent lower than the first dielectric constant.

11. An integrated circuit as claimed in claim 10 wherein the effective dielectric constant is approximately 2.5.

12. An integrated circuit comprising:

a low resistivity, semiconductor substrate including an active region and a dielectric region;

at least one active component positioned in the active region;

a trench formed in the dielectric region and including side-walls defined by low dielectric constant material;

high conductivity electroplated material in the trench and defining at least a portion of a passive electronic component; and

further including a cavity at least partially defined by the substrate in the dielectric region and in communication with a lower portion of the high conductivity, electroplated material in the trench.

13. An integrated circuit as claimed in claim 12 and further including a die attach pad with a pedestal formed on a surface thereof, the substrate being mounted on the die attach pad with the pedestal positioned in the cavity so as to seal the cavity.

14. An integrated circuit comprising:

a low resistivity, semiconductor substrate including an active region and a dielectric region;

at least one active component positioned in the active region;

an elongated trench formed in the dielectric region and including side-walls defined by low dielectric constant material;

high conductivity material in the trench and defining at least a portion of an inductive component; and

a sealed cavity at least partially defined by the substrate in the dielectric region and in communication with a lower portion of the high conductivity material in the trench.

15. An integrated circuit as claimed in claim 14 wherein the sealed cavity is sealed by a die attach pad with a pedestal formed on a surface thereof, the substrate being mounted on the die attach pad with the pedestal positioned in the cavity so as to seal the cavity.

16. An integrated circuit as claimed in claim 15 wherein the cavity defines a distance between the lower portion of the high conductivity material and the pedestal of approximately one hundred micrometers.

17. An integrated circuit as claimed in claim 14 wherein the low dielectric constant material of the side-walls has an effective dielectric constant of approximately 2.5.