Digital delay device, digital oscillator clock signal generator and memory interface

• US 7,148,728 B2
• Filed: 10/01/2004
• Issued: 12/12/2006
• Est. Priority Date: 10/01/2003
• Status: Expired due to Fees

• Current Assignee: Qualcomm Technologies Incorporated (Qualcomm, Inc.)
• Original Assignee: Arteris SAS (Arteris Incorporated)
• Inventors: Boucard, Philippe, Lecler, Jean-Jacques, Montperrus, Luc
• Primary Examiner(s): NGUYEN, LINH M
• Application Number:
  US10/957,211
• Publication Number:
  US 20050104644A1
• Time in Patent Office: 802 Days
• Field of Search: 327/149, 327/153, 327/150, 327/161, 327261-265, 327276-279, 327/158, 331/17, 331/25, 375/373, 375/375, 375/376, 375/374
• US Class Current: 327/149
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.

Claims

1. Digitally controlled delay device comprising a plurality of fine delay elements and a plurality of coarse delay elements, configured to delay a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays, the sum of the fine delay times being greater than or equal to any one of the coarse delays, the coarse delay elements having delay times spaced in such a way that the sum of the fine delay times is greater than or equal to the difference between two adjacent combinations of coarse delay times, and comprising an element for the control and management of the fine delay elements, configured to activate or to deactivate the fine delay elements and coarse delay elements, according to an output of a frequency locked loop.

2. The device of claim 1, wherein the fine delay elements have delay times of between 86% and 116% of the mean of the fine delays.

3. The device of claim 1, wherein the fine delay elements have delay times of between 90% and 110%.

4. The device of claim 1, wherein the coarse delay elements have delay times having the same relative accuracy as the fine delays.

5. The device of claim 1, wherein the control and management element of the fine delay carries out activation of a coarse delay element without modification of the fine delay elements, and the control and management element of the fine delay carries out deactivation of a coarse delay element while activating fine delay elements in order to prevent a large change in the sum of the delays.

6. The device of claim 5, wherein the control and management element comprises a means of synchronization of the control of the fine delay elements and of the coarse delay elements.

7. The device of claim 1, wherein at least one fine delay element comprises an active component provided with a capacitance, the delay variation being due to the Miller effect.

8. The device of claim 7, wherein the fine delay element comprises means of activation and of partial deactivation of the capacitance.

9. The device of claim 7, wherein the fine delay element comprises a gate with at least two inputs.

10. The device of claim 9, wherein the gate comprises an isolated output.

11. The device of claim 9, wherein the gate comprises a delay adjustment control input.

12. The device of claim 7, wherein the fine delay element comprises an inverter.

13. The device of claim 7, further comprising a plurality of coupled fine delay elements.

14. The device of claim 1, further comprising a means of counting a fractional part of a reference clock period.

15. Memory interface comprising two devices according to claim 1, one of the devices being looped back.

16. Interface according to claim 15, wherein the two devices are coupled to a same control.