Single transistor vertical memory gain cell
First Claim
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1. A method for operating a memory cell, comprising:
- providing a vertical transistor having a source, a drain, and a floating body region therebetween, a gate opposing the floating body region and separated therefrom by a gate oxide on a first side of the vertical transistor, and a floating body back gate opposing the body region on a second side of the vertical transistor; and
modulating a threshold voltage and a conductivity of the vertical transistor using the floating body back gate.
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Abstract
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor and is separated therefrom by a dielectric to form a body capacitor.
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Citations
27 Claims
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1. A method for operating a memory cell, comprising:
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providing a vertical transistor having a source, a drain, and a floating body region therebetween, a gate opposing the floating body region and separated therefrom by a gate oxide on a first side of the vertical transistor, and a floating body back gate opposing the body region on a second side of the vertical transistor; and modulating a threshold voltage and a conductivity of the vertical transistor using the floating body back gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for operating a memory cell, comprising:
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providing a vertical transistor having a source, a drain, and a floating body region therebetween, a gate opposing the floating body region and separated therefrom by a gate oxide on a first side of the vertical transistor, and a floating body back gate opposing the body region on a second side of the vertical transistor; modulating a threshold voltage and a conductivity of the vertical transistor using the floating body back gate; storing a first state on the floating body, including; grounding the floating body back gate and the source; and applying a positive voltage to both the gate and the drain; storing a second state on the floating body, including; grounding the floating body back gate and the source; applying a positive voltage to the gate; and applying a negative voltage to the drain; providing a standby state, wherein the standby state includes; applying a negative voltage to the gate; and driving the floating body region to a negative potential by virtue of a capacitive coupling of the floating body region to the gate. - View Dependent Claims (11)
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12. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region;
- and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;
applying a reference potential to the floating body back gate; storing a first memory state, including operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region; and storing a second memory state, including forward biasing a junction between the drain and floating body region of the vertical transistor to remove collected holes in the floating body region. - View Dependent Claims (13, 14, 15, 16, 17, 18)
- and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;
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19. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region;
- and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;
applying a reference potential to the floating body back gate; storing a first memory state, including operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region, including driving the gate with a positive potential while driving the drain with a positive potential; and storing a second memory state, including forward biasing a junction between the drain and floating body region to remove collected holes in the floating body region, including driving the gate with a positive potential while driving the drain with a negative potential. - View Dependent Claims (20, 21)
- and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;
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22. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region;
- and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;
applying a reference voltage to the floating body back gate; storing a first memory state, including operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region; storing a second memory state, including forward biasing a junction between the drain and floating body region to remove collected holes in the floating body region; holding a memory state, including driving the gate to lower a potential of the floating body region through capacitive coupling between the floating body region and the gate; and reading a stored memory state, including sensing a drain current. - View Dependent Claims (23, 24, 25)
- and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;
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26. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region;
- and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;
storing a first memory state, including; applying a ground potential to the floating body back gate which is capacitively coupled to the floating body region; and applying a positive potential to the gate and to the drain to induce avalanche breakdown and hole collection in the floating body region; reading the stored first state in the memory cell, including sensing a drain current indicative of stored charge in the floating body region; storing a second memory state, including; applying a ground potential to the floating body back gate which is capacitively coupled to the floating body region; applying a positive potential to the gate while applying a negative potential to the drain; and maintaining a stored state during standby, including applying a negative potential to the gate to lower the potential of the floating body region. - View Dependent Claims (27)
- and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;
Specification