Single transistor vertical memory gain cell

• US 7,149,109 B2
• Filed: 08/30/2004
• Issued: 12/12/2006
• Est. Priority Date: 08/29/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US10/929,307
• Publication Number:
  US 20050041457A1
• Time in Patent Office: 834 Days
• Field of Search: 365/174, 365/145, 365/185.05, 365/185.18, 365/185.2
• US Class Current: 365/174
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor and is separated therefrom by a dielectric to form a body capacitor.

Claims

1. A method for operating a memory cell, comprising:

providing a vertical transistor having a source, a drain, and a floating body region therebetween, a gate opposing the floating body region and separated therefrom by a gate oxide on a first side of the vertical transistor, and a floating body back gate opposing the body region on a second side of the vertical transistor; and

modulating a threshold voltage and a conductivity of the vertical transistor using the floating body back gate.

2. The method of claim 1, wherein the method includes storing a first state on the floating body, wherein storing a first state on the floating body includes:

grounding the floating body back gate and the source; and

applying a positive voltage to both the gate and the drain.

3. The method of claim 2, wherein grounding and applying include causing avalanche breakdown such that holes are generated and collect on the floating body region.

4. The method of claim 1, wherein the method includes storing a charge on the floating body, wherein storing a charge on the floating body includes:

biasing the source to a positive potential;

grounding the floating body back gate; and

applying a negative potential to the gate.

5. The method of claim 4, wherein biasing, grounding and applying include driving the floating body region and a source drain junction to a reverse bias.

6. The method of claim 1, wherein the method includes increasing a capacitance of the floating body region and enabling a charge storage on the floating body region.

7. The method of claim 1, wherein providing a vertical transistor includes providing an n-channel MOS transistor (NMOS).

8. The method of claim 1, wherein the method further includes providing a standby state, wherein the standby state includes:

applying a negative voltage to the gate; and

driving the floating body region to a negative potential by virtue of a capacitive coupling of the floating body region to the gate.

9. The method of claim 1, wherein method includes storing a second state on the floating body, wherein storing a second state on the floating body includes:

grounding the floating body back gate and the source;

applying a positive voltage to the gate; and

applying a negative voltage to the drain.

10. A method for operating a memory cell, comprising:

providing a vertical transistor having a source, a drain, and a floating body region therebetween, a gate opposing the floating body region and separated therefrom by a gate oxide on a first side of the vertical transistor, and a floating body back gate opposing the body region on a second side of the vertical transistor;

modulating a threshold voltage and a conductivity of the vertical transistor using the floating body back gate;

storing a first state on the floating body, including;

grounding the floating body back gate and the source; and

applying a positive voltage to both the gate and the drain;

storing a second state on the floating body, including;

grounding the floating body back gate and the source;

applying a positive voltage to the gate; and

applying a negative voltage to the drain;

providing a standby state, wherein the standby state includes;

applying a negative voltage to the gate; and

driving the floating body region to a negative potential by virtue of a capacitive coupling of the floating body region to the gate.

11. The method of claim 10, further comprising reading a stored memory state, including sensing a drain current.

12. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region;

and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;

applying a reference potential to the floating body back gate;

storing a first memory state, including operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region; and

storing a second memory state, including forward biasing a junction between the drain and floating body region of the vertical transistor to remove collected holes in the floating body region.

13. The method of claim 12, wherein operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region includes driving the gate with a positive potential while driving the dram with a positive potential.

14. The method of claim 12, wherein forward biasing a junction between the drain and floating body region to remove collected holes in the floating body region includes driving the gate with a positive potential while driving the drain with a negative potential.

15. The method of claim 12, further comprising holding a memory state, including driving the gate with a negative potential.

16. The method of claim 15, wherein driving the gate with a negative potential drive the floating body region to a negative potential due to capacitive coupling between the gate and the floating body region.

17. The method of claim 12, further comprising reading a stored memory state, including sensing a drain current, wherein the first memory state with holes collected in the floating body region results in a larger drain current than the second memory state with holes removed from the floating body region.

18. The method of claim 12, further comprising applying a reference voltage to the floating body back gate.

19. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region;

and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;

applying a reference potential to the floating body back gate;

storing a first memory state, including operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region, including driving the gate with a positive potential while driving the drain with a positive potential; and

storing a second memory state, including forward biasing a junction between the drain and floating body region to remove collected holes in the floating body region, including driving the gate with a positive potential while driving the drain with a negative potential.

20. The method of claim 19, wherein driving the gate with a positive potential includes applying a pulse of approximately 1 V to the gate, driving the drain with a positive potential includes applying a pulse of approximately 1.5 V to the drain, and driving the drain with a negative potential includes applying a pulse of approximately −

0.5 V to the drain.

21. The method of claim 19, further comprising holding a memory state, including applying a potential of about −

1 V to the gate.

22. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region;

and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;

applying a reference voltage to the floating body back gate;

storing a first memory state, including operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region;

storing a second memory state, including forward biasing a junction between the drain and floating body region to remove collected holes in the floating body region;

holding a memory state, including driving the gate to lower a potential of the floating body region through capacitive coupling between the floating body region and the gate; and

reading a stored memory state, including sensing a drain current.

23. The method of claim 22, further comprising applying the reference voltage to the source.

24. The method of claim 22, wherein:

operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region includes driving the gate with a positive potential while driving the drain with a positive potential; and

forward biasing a junction between the drain and floating body region to remove collected holes in the floating body region includes driving the gate with a positive potential while driving the drain with a negative potential.

25. The method of claim 22, wherein holding a memory state further includes applying a positive voltage to the source when the gate is driven to a negative voltage.

26. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region;

and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising;

storing a first memory state, including;

applying a ground potential to the floating body back gate which is capacitively coupled to the floating body region; and

applying a positive potential to the gate and to the drain to induce avalanche breakdown and hole collection in the floating body region;

reading the stored first state in the memory cell, including sensing a drain current indicative of stored charge in the floating body region;

storing a second memory state, including;

applying a ground potential to the floating body back gate which is capacitively coupled to the floating body region;

applying a positive potential to the gate while applying a negative potential to the drain; and

maintaining a stored state during standby, including applying a negative potential to the gate to lower the potential of the floating body region.

27. The method of claim 26, wherein maintaining a stored state during standby further includes applying a positive potential to the source.