Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery

• US 7,149,269 B2
• Filed: 02/27/2003
• Issued: 12/12/2006
• Est. Priority Date: 02/27/2003
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cranford, Hayden C. Jr., Schmatz, Martin, Norman, Vernon R.
• Primary Examiner(s): Ghayour, Mohammed
• Assistant Examiner(s): File, Erin M.
• Application Number:
  US10/375,286
• Publication Number:
  US 20040170244A1
• Time in Patent Office: 1,384 Days
• Field of Search: 375/373, 375/371, 375/354, 327/1, 709/248, 714/12
• US Class Current: 375/373
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0998 using phase interpolation
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A receiver for clock and data recovery includes n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (φ1a . . . (φna) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (φ1a . . . φna), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (φ1u . . . φnu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (φ1a . . . φna) depending on the sampling phases (φ1u . . . φnu) and said adjusting signal (AS).

Claims

1. A receiver for clock and data recovery, comprising

n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (j1a . . . jna), having sampling latch inputs and sampling latch outputs,

a phase position analyzer (5) connected to said sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (j1a . . . jna), if the sample value (SV1 . . . SVn) deviates from a set point,

a phase interpolator (9) for generating sampling phases (j1u . . . jnu),

a sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) for generating adjusted sampling phases (j1a . . . jna) depending on said sampling phases (j1u . . . jnu) and said adjusting signal (AS),

a sample memory (4) for storing the sampled values (SV1 . . . SVn) and connected between the sample latches (SL1 . . . SLn) and the phase position analyzer (5),

a data output (OUT) for delivering parallel data (DP) and connected to the sample memory (4), and

an edge detection unit (8) for detecting edges in a serial data signal (DS) and connected between the sample memory (4) and a control input of the phase interpolator (9).

2. Receiver according to claim 1,

wherein the phase position analyzer (5) comprises means for determining average values (AV1 . . . AVn) of the sample values (SV1 . . . SVn).

3. Receiver according to claims 1 or 2,

comprising a data input (IN1) for receiving said serial data (DS), which shall be recovered, and comprising switching means (11) connected to the sampling latch inputs, wherein said switching means (11) are provided for leading said serial data (DS) or the reference signal (Ref2) to the said sampling latch inputs.

4. Receiver according to claims 1 or 2,

wherein the reference signal (Ref2) has a constant phase and a constant frequency.

5. Receiver according to claim 2,

wherein the phase position analyzer (5) comprises means for increasing the adjusting signal (AS), if the average value (AV1, . . . AVn) is lower than a set point, and for decreasing the adjusting signal (AS), if the average value (AV1, . . . AVn) is higher than said set point.

6. Receiver according to claim 1,

wherein the sampling phase adjusting unit (6) comprises a buffer (41) or inverter with a programmable delay time.

7. Receiver according to claim 1,

wherein the sampling phase adjusting unit (6) comprises a phase interpolating device (42) for interpolating two consecutive sample phases.

8. Receiver according to claim 7,

wherein the interpolating device comprises first and second means (44, 45) for weighting the two sample phases.

9. Receiver according to claim 1,

wherein the sampling phase adjusting unit (6) comprises a phase interpolating device (46) for interpolating three sample phases, wherein one of these is a nominal sampling phase superimposed by the two other phases.

10. Method for calibrating sampling phases in a receiver for clock and data recovery, comprising the following steps of:

a reference signal (Ref2) is led to n sampling latches (SL1 . . . SLn),

the reference signal (Ref2) is sampled at different sampling phases (j1u . . . jnu) and the corresponding sample values (SV1 . . . SVn) are determined with said sampling latches (SL1 . . . SLn),

the sampled values are stored within a sample memory (4) connected between the sample latches (SL1 . . . SLn) and a phase position analyzer (5),

parallel data (DP) is delivered from a data output (OUT) connected to the sample memory (4),

edges in a serial data signal (DS) are detected by an edge detection unit (8) connected between the sample memory (4) and a control input of a phase interpolator (9), and

if said sample value (SV1 . . . SVn) deviates from a set point, the corresponding sampling phase (j1u . . . jnu) is corrected.

11. Method according to claim 10,

wherein the reference signal (Ref2) is led to the sampling latches (SL1 . . . SLn) and the receiver is switched to calibration mode, the receiver capable of switching at least between the calibration mode and a recovery mode.

12. Method according to claim 11,

wherein after calibration in the calibration mode is finished said receiver is switched to the recovery mode.

13. Method according to any of the claims 10 or 11,

wherein the determination of the sample values (SV1 . . . SVn) comprises the following steps:

a) the reference signal (Ref2) is sampled s times at a first sample phase position (jlu), wherein the sample value (SV1) of the reference signal (Ref2) is determined each time with the first sample latch (SL1),

b) from the s sample values (SV1) an average value (AV1) is calculated,

c) these steps are repeated at n sampling phases (j2. . .jn), wherein at the nth sampling phase (jn) each sample value (SVn) is determined with the nth sample latch (SLn).

14. Method according to claim 10,

wherein the correction of the sampling phase (j1u, . . . jnu) comprises the following step:

the sampling phase (j1u, . . . jnu) is increased if the average value (AV1, . . . AVn) is lower than 0.5.

15. Method according to claim 10,

wherein the correction of the sampling phase (j1u, . . . jnu) comprises the following step:

the sampling phase (j1u, . . . jnu) is decreased if the average value (AV1, . . . AVn) is higher than 0.5.

16. Method according to claim 10,

further comprising the following steps:

the sampling phases (j1u, . . . jnu) are shifted by a predetermined value,

the reference signal (Ref2) is sampled at said shifted sampling phases (j1u . . . jnu) and the corresponding sample values (SV1 . . . SVn) are determined with said sampling latches (SL1 . . . SLn),

if said sample value (SV1 . . . SVn) deviates from the set point, the corresponding sampling phase (j1u . . . jnu) is corrected, and

these steps are repeated as often as it is necessary for synchronizing all sampling phases (j1u . . . jnu) with the reference signal (Ref2).