Multistandard video decoder and decompression system for processing encoded bit streams including a reconfigurable processing stage and methods relating thereto

• US 7,149,811 B2
• Filed: 01/30/2001
• Issued: 12/12/2006
• Est. Priority Date: 06/30/1992
• Status: Expired due to Fees

• Current Assignee: Chartoleaux KG LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Robbins, William P, Wise, Adrian P, Boyd, Kevin J, Sotheran, Martin W, Claydon, Anthony Peter J, Finch, Helen R, Jones, Anthony M
• Primary Examiner(s): Jean, Frantz B.
• Application Number:
  US09/772,698
• Publication Number:
  US 20030227969A1
• Time in Patent Office: 2,142 Days
• Field of Search: 709245-247, 712 15- 18, 712/209, 712/300, 382/232, 382/233, 382/235, 382/166, 382/246, 382/303, 375/240.01, 375/240.25, 710/68, 715/500.1
• US Class Current: 709/247
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream, A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token.

Claims

1. A multiple stage processing pipeline for handling bit streams encoded in accordance with different standards and arranged as a single serial bit stream, the multiple stage processing pipeline comprising:

a token generator responsive to the single serial bit stream for generating at least one token;

at least one reconfigurable processing stage to receive said at least one token; and

a parser in said at least one reconfigurable processing stage configured to respond to said at least one token by enabling for processing different portions of the single serial bit stream corresponding to different ones of the different standards.

2. The multiple stage processing pipeline of claim 1, wherein the at least one reconfigurable processing stage comprises:

a token decoder for recognizing the token as a control token pertinent to that at least one reconfigurable processing stage and for passing said token to another of the stages if said token is an unrecognized one.

3. The multiple stage processing pipeline of claim 2, wherein the at least one reconfigurable processing stage further comprises:

an action identification unit responsive to the control token for reconfiguring the at least one reconfigurable processing stage to process a data token identified by the at least one token according to one of the different standards.

4. The multiple stage processing pipeline of claim 3, wherein the token generator, the action identification unit and the token decoder are implemented in hardware.

5. The multiple stage processing pipeline of claim 1, wherein the different standards include MPEG.

6. The multiple stage processing pipeline of claim 1, wherein the different standards include JPEG.

7. The multiple stage processing pipeline of claim 1, wherein the different standards include H.261.

8. The multiple stage processing pipeline of claim 1, wherein the at least one reconfigurable processing stage comprises a spatial decoding stage.

9. The multiple stage processing pipeline of claim 1, wherein the at least one reconfigurable processing stage comprises a temporal decoding stage.

10. The multiple stage processing pipeline of claim 9, wherein the temporal decoding stage comprises a reconfigurable prediction filters block.

11. The multiple stage processing pipeline of claim 10, wherein the token comprises a coding standard token and wherein the reconfigurable prediction filters block is reconfigured in response to the coding standard token.

12. The multiple stage processing pipeline of claim 11, wherein the token comprises a prediction mode token and wherein the reconfigurable prediction filters block operates in accordance with the mode specified in the prediction mode token.

13. The multiple stage processing pipeline of claim 1, wherein the at least one reconfigurable processing stage comprises reconfigurable processing stages including at least one spatial decoding stage and at least one temporal decoding stage.

14. A method for handling bit streams encoded in accordance with different standards and arranged as a single serial bit stream comprising:

generating tokens in response to the single serial bit stream;

recognizing certain of the generated tokens as control tokens;

parsing the control tokens to reconfigure the at least one reconfigurable processing stage; and

processing different portions of the single serial bit stream in the reconfigurable processing stage corresponding to different ones of the standards in response to the generated tokens.

15. The method of claim 14, wherein the different standards include JPEG.

16. The method of claim 14, wherein the different standards include MPEG.

17. The method of claim 14, wherein the different standards include H.261.

18. A system comprising:

a detector unit for receiving a data stream of data having portions encoded according to different standards and for generating tokens based on respective portions of the received data stream;

a parser to process the tokens and to reconfigure at least one reconfigurable processing stage in response to the token; and

a processor configured to respond to the generated tokens by processing the respective portions of the data stream corresponding to different standards to produce a decoded output using the processing stage reconfigured by the parser.

19. The system of claim 18, wherein the processor comprises a pipeline processor having at least one reconfigurable processing stage.

20. The system of claim 19, further comprising:

a token decoder for recognizing ones of the generated tokens as control tokens pertinent to that at least one reconfigurable processing stage.

21. The system of claim 19, wherein the at least one reconfigurable processing stage comprises:

an action identification unit responsive to at least one of the control tokens for reconfiguring the at least one reconfigurable processing stage to process a data token identified by the at least one control token according to one of the different standards.

22. The system of claim 18, wherein the different standards include MPEG.

23. The system of claim 18, wherein the different standards include JPEG.

24. The system of claim 18, wherein the different standards include H.261.