System and method for direct memory access from host without processor intervention wherein automatic access to memory during host start up does not occur

• US 7,149,823 B2
• Filed: 08/29/2003
• Issued: 12/12/2006
• Est. Priority Date: 08/29/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Emulex Corporation (Broadcom, Inc.)
• Inventors: Tang, John Sui-Kei, Duckman, David James, Miller, Eddie, Butler, Jim Donald, Jin, Daming
• Primary Examiner(s): Peyton, Tammara
• Application Number:
  US10/651,887
• Publication Number:
  US 20050050245A1
• Time in Patent Office: 1,201 Days
• Field of Search: 710/22, 710/27, 710/74, 710/305, 710/306, 710/36, 713/1, 713/2
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a preferred embodiment, new host registers are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to access the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.

Claims

1. A method of providing programmed direct access to peripheral memory located on a peripheral device including a microprocessor and controller circuitry by a host device, via a bus interface, comprising:

writing an address to a host-configured address register located on the peripheral device, wherein the address is generated and transmitted by host software executed by the host device via the bus interface; and

accessing the peripheral memory at a location corresponding to the address written in the host address register by the controller circuitry without burdening the microprocessor, wherein said accessing does not occur as part of an automatic access to the peripheral memory during host device start up.

2. The method of claim 1 wherein said bus interface is not locked if said act of accessing is waiting for other access requests to the peripheral memory to be completed.

3. The method of claim 1 wherein said act of accessing comprises:

retrieving data from said location corresponding to said address;

storing the retrieved data in a host-configured data register located on said peripheral devices, by the peripheral device'"'"'s controller circuitry; and

reading the retrieved data from the host-configured data register so as to transmit the data directly to said host device, wherein the read operation is performed by said host software.

4. The method of claim 3 further comprising:

retrieving additional data from a next sequential address location within said peripheral memory;

storing the additional data in said host-configured data register;

reading the additional data from the host-configured data register so as to transmit the data directly to said host device; and

repeating the steps of retrieving, storing and reading additional data until data from a last sequential data address is retrieved, stored and read, wherein said read operations are performed by said host software.

5. The method of claim 1 wherein said act of accessing comprises:

writing data to a host-configured write register located on said peripheral device, wherein the data is transmitted by said host software executed by said host device; and

;

writing the data to said location in said peripheral memory, wherein controller circuitry within the peripheral device writes the data to the peripheral memory without burdening the microprocessor.

6. The method of claim 1 wherein said host device comprises a server, said peripheral device comprises a host bus adapter card, said peripheral memory comprises a flash memory device, and said bus interface comprises a PCI/PCIX bus interface.

7. A method of providing a host device programmed direct access to peripheral memory located on a peripheral device including a microprocessor and controller circuitry, comprising:

mapping a plurality of registers to host configuration space so as to allow host software executed by the host device to read and write to the plurality of registers, wherein the plurality of registers are located on the peripheral device and comprises an address register and a data register; and

writing a desired address in the address register, wherein the host software generates the desired address and writes it in the address register, thereby causing controller circuitry within the peripheral device to automatically access the peripheral memory at a location corresponding to the desired address without burdening the microprocessor, wherein said act of writing occurs after host device start operations have been completed.

8. The method of claim 7 wherein said controller circuitry automatically retrieves data stored at said location in peripheral memory and stores the data in said data register, the method further comprising reading the data from the data register by said host software.

9. The method of claim 7 further comprising writing data to said data register, thereby causing said controller circuitry to automatically store the data in said peripheral memory at said location without burdening the microprocessor.

10. A system for providing direct host device access comprising:

a host device comprising host software and being configured to execute said software;

a peripheral device further comprising;

a peripheral memory;

a microprocessor connected to the peripheral memory;

means for writing an address to a host-configured address register located on the peripheral device, wherein the address is generated and transmitted by the host software executed by the host device after host device start up operations are completed; and

a controller circuitry connected to the peripheral memory configured for accessing the peripheral memory at a location corresponding to the address written in the host address register without burdening the microprocessor.

11. The system of claim 10 wherein said means for accessing comprises:

means for retrieving data from said location corresponding to said address;

means for storing the retrieved data in a host-configured data register located on said peripheral device; and

means for reading the retrieved data from the host-configured data register so as to transmit the data directly to said host device, wherein the read operation is performed by said host software.

12. The system of claim 11 further comprising:

means for retrieving additional data from a next sequential address location within said peripheral memory;

means for storing the additional data in said host-configured data register;

means for reading the additional data from the host-configured data register so as to transmit the data directly to said host device; and

means for repeating the steps of retrieving, storing and reading additional data until data from a last sequential data address is retrieved, stored and read, wherein said read operations are performed by said host software.

13. The system of claim 10 wherein means for accessing comprises:

means for writing data to a host-configured write register located on said peripheral device, wherein the data is transmitted by said host software executed by said host device; and

;

means for writing the data to said location in said peripheral memory, wherein controller hardware within the peripheral device writes the data to the peripheral memory.

14. The system of claim 10 wherein said host device comprises a server, said peripheral device comprises a host bus adapter card, said peripheral memory comprises a flash memory device, and said means for writing and said means for accessing comprise a PCI/PCIX bus interface.

15. A computer readable storage device, for storing computer-executable instructions that when executed perform a method of providing a host device programmed direct access to peripheral memory located on a peripheral device including a microprocessor and control circuitry, the method comprising:

mapping a plurality of registers to host configuration space so as to allow host software executed by the host device to read and write to the plurality of registers, wherein the plurality of registers are located on the peripheral device and comprises an address register and a data register; and

writing a desired address in the address register, wherein the host software generates the desired address and writes it in the address register, thereby causing the controller circuitry within the peripheral device to automatically access the peripheral memory at a location corresponding to the desired address without burdening the microprocessor, wherein said writing occurs after start up operations for said host device have been completed.

16. The computer-readable storage device of claim 15 wherein said controller circuitry retrieves data stored at said location in peripheral memory and stores the data in said data register, and said method further comprises reading the data from the data register by said host software.

17. The computer-readable storage device of claim 15 wherein said method further comprises writing data to said data register, thereby causing said controller circuitry to store the data in said peripheral memory at said location without burdening the microprocessor.