System and method for signal delay in an adaptive voltage scaling slack detector

• US 7,149,903 B1
• Filed: 12/18/2002
• Issued: 12/12/2006
• Est. Priority Date: 12/18/2002
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Cameron, Donald Kevin, Chan, Wai Cheong
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Bae, Ji H.
• Application Number:
  US10/324,997
• Time in Patent Office: 1,455 Days
• Field of Search: 713/300, 377/129
• US Class Current: 713/300
• CPC Class Codes: H03K 27/00 Pulse counters in which pulses are continuously circulated in a closed loop; Analogous frequency dividers feedback shift register counters H03K23/54

Abstract

A system and method for slack determination in a logic integrated circuit. A launch pulse is input to a circular delay loop circuit. The leading edge of the launch pulse causes a pulse to circulate around the circular delay loop. The number of passes made through the loop by the circulating pulse is counted by a latch/counter circuit. A sample pulse is input to the latch/counter circuit to latch the number of pulse circulations at the leading edge of the sample pulse. The pulse circulation count provides delay information in the circuit that may subsequently be used to adjust a supply voltage in the integrated circuit.

Claims

1. A system for signal delay in an adaptive voltage scaling slack detector comprising:

an adjustable voltage supply;

a resetable delay loop circuit comprising a launch input and a first reset input, said launch input for receiving a launch pulse waveform, wherein said resetable delay loop circuit circulates a pulse in response to receiving said launch pulse waveform; and

a resetable counter/latch circuit comprising a second reset input, an output, an input coupled to an output of said resetable delay loop circuit, and a sample input, said counter/latch circuit for counting the number of times said pulse circulates in said resetable delay loop circuit, said sample input for receiving a sample pulse waveform, wherein said sample pulse waveform causes said resetable counter/latch to latch a pulse circulation count, wherein said adjustable voltage supply is adjusted based on said pulse circulation count.

2. The system of claim 1, further comprising an OR gate, said OR gate comprising a first input coupled to said sample input, a second input coupled to said second reset input, and an output coupled to said first reset input.

3. The system of claim 1, wherein said resetable delay loop circuit comprises:

a resetable delay element comprising a delay input, a reset input, and a delay output;

an XOR gate comprising a first input coupled to said launch input, a second input coupled to said delay output, and an output coupled to said delay input.

4. The system of claim 1, wherein said resetable delay loop circuit comprises:

an edge detector/pulse generator coupled to said launch input and to said first reset input;

a delay element coupled to said launch input;

a first multiplexer comprising a first switched input coupled to an output of said edge detector/pulse generator, and a control input coupled to an output of said delay element;

a pulse regenerator coupled to said first reset input and to a second switched input of said first multiplexer; and

a resetable delay element coupled to said first reset input, to an output of said first multiplexer, and to said pulse regenerator.

5. The system of claim 4, wherein said edge detector/pulse generator comprises:

an inverter coupled to said launch input;

a second multiplexer coupled to said inverter and to said launch input; and

a flip-flop coupled to a control input of said second multiplexer, and to an output of said second multiplexer.

6. The system of claim 1, wherein said sample input is coupled to said first reset input.

7. The system of claim 1, wherein said launch input is coupled to said second reset input.

8. A logic integrated circuit comprising:

an adjustable voltage supply;

an adjustable timing clock;

control logic for adjusting said adjustable voltage supply and said adjustable timing clock;

a delay loop circuit for circulating a pulse in response to receiving a launch pulse waveform; and

a counting and latching circuit coupled to said control logic and an output of said delay loop circuit, said counting and latching circuit for counting the number of times said pulse circulates in said delay loop circuit, wherein said counting and latching circuit latches a pulse circulation count upon receiving a sample pulse waveform, wherein said control logic adjusts said adjustable voltage supply based on said pulse circulation count.

9. The logic integrated circuit of claim 8, wherein said delay loop circuit comprises a multiplexer.

10. The logic integrated circuit of claim 8, wherein said delay loop circuit comprises an edge detector/pulse generator circuit.

11. The logic integrated circuit of claim 8, wherein said delay loop circuit comprises a launch input and a sample input.

12. The logic integrated circuit of claim 8, wherein said counting and latching circuit comprises a launch input and a sample input.

13. The logic integrated circuit of claim 8, wherein said delay loop circuit comprises an XOR gate coupled to a regenerative delay element.

14. The logic integrated circuit of claim 8, wherein said delay loop circuit comprises a standard cell.

15. A method for adaptive voltage scaling in an integrated circuit comprising an adjustable voltage supply with a value V_DD in response to a frequency change of a master clock, comprising:

applying a launch pulse waveform to a circular delay loop circuit, thereby causing a pulse to circulate in said delay loop circuit;

counting the number of times said pulse circulates in said delay loop circuit with a counter/latch circuit;

applying a sample pulse waveform to said counter/latch circuit to latch a pulse circulation count in said counter/latch circuit; and

adjusting said adjustable voltage supply based on said pulse circulation count.

16. The method of claim 15, further comprising comparing said pulse circulation count to a predetermined slack threshold value.

17. The method of claim 16, further including increasing V_DD by a predetermined amount if said pulse circulation count is less than said slack threshold value.

18. The method of claim 16, further including decreasing V_DD by a predetermined amount if said pulse circulation count is greater than said slack threshold value.

19. The method of claim 17 wherein said launch pulse waveform overlaps said sample pulse waveform.

20. The method of claim 15, wherein said launch pulse waveform leads said sample waveform by ninety degrees.