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Systems and methods for providing error correction code testing functionality

  • US 7,149,945 B2
  • Filed: 05/09/2003
  • Issued: 12/12/2006
  • Est. Priority Date: 05/09/2003
  • Status: Active Grant
First Claim
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1. A memory controller, comprising:

  • a cache line processing block for processing a cache line into a plurality of segments;

    an error correction code (ECC) generation block that forms ECC code words for each of said plurality of segments for storage in a plurality of memory components;

    an ECC correction block for correcting at least one single-byte erasure error in each erasure corrupted ECC code word retrieved from said plurality of memory components; and

    an error seeding block that enables a respective error to be inserted into each ECC code word of said cache line in response to a plurality of error registers.

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