Systems and methods for providing error correction code testing functionality

• US 7,149,945 B2
• Filed: 05/09/2003
• Issued: 12/12/2006
• Est. Priority Date: 05/09/2003
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Brueggen, Christopher M.
• Primary Examiner(s): Lamarre, Guy J.
• Application Number:
  US10/435,149
• Publication Number:
  US 20040225943A1
• Time in Patent Office: 1,313 Days
• Field of Search: 714/758, 714/769, 714/756, 714/784
• US Class Current: 714/758
• CPC Class Codes: H03M 13/01 Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

Abstract

In one embodiment, a memory controller comprises a cache line processing block for processing a cache line into a plurality of segments, an error correction code (ECC) generation block that forms ECC code words for each of the plurality of segments for storage in a plurality of memory components, an ECC correction block for correcting at least one single-byte erasure error in each erasure corrupted ECC code word retrieved from the plurality of memory components, and an error seeding block that enables a respective error to be inserted into each ECC code word of the cache line in response to a plurality of error registers.

Claims

1. A memory controller, comprising:

a cache line processing block for processing a cache line into a plurality of segments;

an error correction code (ECC) generation block that forms ECC code words for each of said plurality of segments for storage in a plurality of memory components;

an ECC correction block for correcting at least one single-byte erasure error in each erasure corrupted ECC code word retrieved from said plurality of memory components; and

an error seeding block that enables a respective error to be inserted into each ECC code word of said cache line in response to a plurality of error registers.

2. The memory controller of claim 1 wherein said error seeding block seeds errors in said ECC code words before said ECC code words are written to said plurality of memory components.

3. The memory controller of claim 1 wherein ones of said plurality of error registers define respective error patterns to be inserted into said ECC code words.

4. The memory controller of claim 3 wherein even nibbles of an ECC code word are communicated over a bus during a first bus cycle and odd nibbles are communicated over said bus during a second bus cycle, and wherein said error seeding block comprises a counter structure to control application of even nibbles of said error patterns and odd nibbles of said error patterns.

5. The memory controller of claim 1 further wherein one of said plurality of error registers identifies that only a predetermined number of ECC code words are to be corrupted.

6. The memory controller of claim 5 wherein said an error seeding block sets a flag to indicate that said predetermined number of ECC code words have been corrupted and written to said plurality of memory components.

7. The memory controller of claim 1 wherein said error seeding block inserts at least one error into one of said ECC code words of said cache line into addition to said respective errors in each of said ECC code words.

8. A method for operating a memory controller, comprising:

processing a cache line into a plurality of segments;

generating ECC code words for each of said plurality of segments;

seeding a respective error into each ECC code word of said cache line in response to a plurality of error registers of said memory controller;

storing said ECC code words in a plurality of memory components;

retrieving said ECC code words from said plurality of memory components; and

validating an ECC algorithm by attempting to correct each respective inserted error of said ECC code words as an erasure error.

9. The method of claim 8 wherein said seeding inserts respective errors according to at least one error pattern defined in one of said plurality of error registers.

10. The method of claim 9 wherein even nibbles of an ECC code word are communicated over a bus during a first bus cycle and odd nibbles are communicated over said bus during a second bus cycle, and wherein said seeding includes applying even nibbles of said error pattern during a first cycle of said memory controller and applying odd nibbles of said error pattern during a second cycle of said memory controller.

11. The method of claim 8 wherein said seeding emulates a wire failure within a bus in a communication path between said memory controller and said plurality of memory components in response to at least one of said plurality of error registers.

12. The method of claim 8 wherein said seeding emulates a failure of one of said plurality of memory components in response to at least one of said plurality of error registers.

13. The method of claim 8 further comprising:

inserting at least one additional error into one of said ECC code words; and

validating said ECC algorithm by attempting to correct said at least one additional error without specifying to said ECC algorithm a location of said at least one additional error.

14. The method of claim 8 wherein one of said plurality of error registers identifies that only a predetermined number of ECC code words are to be corrupted.

15. The method of claim 14 further comprising:

setting a flag in said memory controller to indicate that said ECC code words have been written to said plurality of memory components.

16. A memory controller, comprising:

means for processing a cache line into a plurality of segments;

means for generating ECC code words for each of said plurality of segments for storage in a plurality of memory components;

means for correcting at least one single-byte erasure error in each erasure corrupted ECC code word retrieved from said plurality of memory components; and

means for inserting a respective error into each ECC code word of said cache line in response to a plurality of error registers, wherein said means for inserting is operable before said means for correcting.

17. The memory controller of claim 16 wherein means for inserting is operable before said ECC code words are written to said plurality of memory components.

18. The memory controller of claim 16 wherein said means for inserting retrieves at least one error pattern from said plurality of error registers to define an error pattern to be applied to said ECC code words.

19. The memory controller of claim 18 wherein said means for inserting communicates even nibbles of an ECC code word over a bus during a first bus cycle and odd nibbles over said bus during a second bus cycle, and wherein said means for inserting inserts even nibbles of said error pattern during a first cycle of said memory controller and inserts odd nibbles of said error pattern during a second cycle of said memory controller.

20. The memory controller of claim 16 wherein means for inserting inserts at least one error into one of said ECC code words of said cache line into addition to said respective errors in each of said ECC code words.