Semiconductor device with improved design freedom of external terminal

• US 7,151,320 B2
• Filed: 11/28/2003
• Issued: 12/19/2006
• Est. Priority Date: 01/08/2003
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Shizuno, Yoshinori
• Primary Examiner(s): Trinh, Michael
• Assistant Examiner(s): BRYANT, KIESHA ROSE
• Application Number:
  US10/722,446
• Publication Number:
  US 20040130022A1
• Time in Patent Office: 1,117 Days
• Field of Search: None
• US Class Current: 257/787
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device comprises: a semiconductor chip having a first main surface, a second main surface, and a plurality of side surfaces; an extension portion which contacts and surrounds the side surfaces of the semiconductor chip; a base, which is capable of conducting heat generated by the semiconductor chip; an insulating film which is formed on the first face and the first main surface; a plurality of wiring patterns extended from electrode pads to the upper side of the first face of the extension portion; a sealing portion which is formed on the wiring patterns and insulating film; and a plurality of external terminals provided over the wiring patterns in a region including the upper side of the extension portion.

Claims

1. A semiconductor device comprising:

a semiconductor chip having a first main surface on which a plurality of electrode pads is provided, a second main surface which opposes said first main surface, and a plurality of side surfaces between said first main surface and said second main surface;

an extension portion which includes a first face and a second face opposing said first face, and which is formed in contact with said side surfaces of said semiconductor chip to thereby surround said semiconductor chip and such that said first face is at a substantially equal level to the level of said first main surface;

a base having a first surface and a second surface which opposes said first surface, said first surface contacting the second face of said extension portion and the second main surface of said semiconductor chip, which is capable of conducting heat generated by said semiconductor chip such that this heat is dispersed into the atmosphere from said second surface side;

an insulating film which is formed on said first face and said first main surface such that a part of each of said plurality of electrode pads is exposed;

a plurality of wiring patterns electrically connected to said electrode pads and extended from said electrode pads to the upper side of the first face of said extension portion, respectively;

a sealing portion which is formed on said wiring patterns and said insulating film such that a part of each of said wiring patterns is exposed; and

a plurality of external terminals provided over said wiring patterns in a region including the upper side of said extension portion;

further comprising a plurality of electrode posts formed between said wiring patterns and said external terminals,

wherein said sealing portion is formed such that the top surface of said electrode posts is exposed;

wherein said electrode posts are formed from a conductive material; and

wherein a thin oxidation layer is formed on the surface of said electrode posts.

2. The semiconductor device according to claim 1, wherein said extension portion is formed from a material having greater molding shrinkage than the molding shrinkage of said sealing portion.

3. The semiconductor device according to claim 1, wherein said extension portion is formed from a liquid resin having a coefficient of linear expansion, within a lower temperature range than a glass transition temperature, of less than 1.5×

10<sup>−

5</sup>/°

C. and a modulus of elasticity within a range of 7.8 to 22 GPa.

4. The semiconductor device according to claim 1, wherein said second face of said base is formed as a three-dimensional construction in which the surface area of said second face is increased.

5. The semiconductor device according to claim 1, wherein said base is formed from a material having a thermal conductivity of at least 150 W/m·

K.

6. The semiconductor device according to claim 1, wherein said base is formed from either a metallic material selected from a group including copper (Cu), aluminum (Al), and a copper/tungsten alloy (CuW), or a ceramic material selected from a group including silicon carbide (SiC) and aluminum nitride (AlN).

7. A semiconductor device comprising:

a semiconductor chip having a first main surface on which a plurality of electrode pads is provided, a second main surface which opposes said first main surface, and a plurality of side surfaces between said first main surface and said second main surface;

an extension portion which includes a first face and a second face opposing said first face, and which is formed in contact with said side surfaces of said semiconductor chip to thereby surround said semiconductor chip and such that said first face is at a substantially equal level to the level of said first main surface;

a base having a first surface and a second surface which opposes said first surface, said first surface contacting the second face of said extension portion and the second main surface of said semiconductor chip, which is capable of conducting heat generated by said semiconductor chip such that this heat is dispersed into the atmosphere from said second surface side;

an insulating film which is formed on said first face and said first main surface such that a part of each of said plurality of electrode pads is exposed;

a plurality of wiring patterns electrically connected to said electrode pads and extended from said electrode pads to the upper side of the first face of said extension portion, respectively;

a sealing portion which is formed on said wiring patterns and said insulating film such that a part of each of said wiring patterns is exposed; and

a plurality of external terminals provided over said wiring patterns in a region including the upper side of said extension portion;

wherein a portion of said wiring patterns on a boundary and vicinity thereof between a region on the upper side of said semiconductor chip and a region of said extension portion is formed wider or more thickly than other portions of said wiring patterns.

8. The semiconductor device according to claim 7, further comprising a plurality of electrode posts formed between said wiring patterns and said external terminals,

wherein said sealing portion is formed such that the top surface of said electrode posts is exposed.

9. The semiconductor chip according to claim 8, wherein said electrode posts are formed from a conductive material.

10. The semiconductor device according to claim 7, wherein said extension portion is formed from a material having greater molding shrinkage than the molding shrinkage of said sealing portion.

11. The semiconductor device according to claim 7, wherein said extension portion is formed from a liquid resin having a coefficient of linear expansion, within a lower temperature range than a glass transition temperature, of less than 1.5×

10<sup>−

5</sup>/°

C. and a modulus of elasticity within a range of 7.8 to 22 GPa.

12. The semiconductor device according to claim 7, wherein said second face of said base is formed as a three-dimensional construction in which the surface area of said second face is increased.

13. The semiconductor device according to claim 7, wherein said base is formed from a material having a thermal conductivity of at least 150 W/m·

K.

14. The semiconductor device according to claim 7, wherein said base is formed from either a metallic material selected from a group including copper (Cu), aluminum (Al), and a copper/tungsten alloy (CuW), or a ceramic material selected from a group including silicon carbide (SiC) and aluminum nitride (AlN).