High PSRR, fast settle time voltage regulator

• US 7,151,363 B1
• Filed: 06/08/2004
• Issued: 12/19/2006
• Est. Priority Date: 06/08/2004
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Nag, Manbir Singh, Scott, Baker
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US10/863,195
• Time in Patent Office: 924 Days
• Field of Search: 323/268, 323/270, 323/271, 323/273, 323/281, 323/282, 323/283, 323/288, 323/313, 323/315
• US Class Current: 323/282
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

Abstract

A voltage regulator including a high-speed feedback loop operating to provide rapid settling time and a large Power Supply Rejection Ratio (PSRR). The high-speed feedback loop includes a reservoir capacitor that stores charge based on a charging current. The charge stored by the reservoir capacitor corresponds to a regulated voltage provided by the voltage regulator. When charge is drawn from the reservoir capacitor by a load, a dip occurs in the regulated output voltage. The high-speed feedback loop operates to restore the charge to the reservoir capacitor, thereby restoring the regulated voltage to its desired value. More specifically, when charge is drawn from the reservoir capacitor, the high-speed feedback loop operates to increase the first current, thereby restoring charge to the reservoir capacitor.

Claims

1. A voltage regulator comprising:

a reservoir capacitance adapted to store charge corresponding to a regulated output voltage, wherein the charge stored by the reservoir capacitance is controlled by a first current;

first circuitry adapted to provide a second current based on the charge stored by the reservoir capacitance;

second circuitry adapted to receive the second current and generate a third current that is inversely related to the second current; and

a current mirror adapted to provide a fourth current based on the third current and a current mirror gain ratio;

the first circuitry further adapted to provide the first current based on the fourth current such that the charge stored by the reservoir capacitance increases when the fourth current increases.

2. The voltage regulator of claim 1 wherein the first current is related to a difference between the fourth current and the second current.

3. The voltage regulator of claim 1 wherein the first current is substantially equal to a difference between the fourth current and the second current.

4. The voltage regulator of claim 1 wherein the first circuitry comprises an output transistor having an input terminal adapted to receive a bias voltage, a second terminal coupled to the reservoir capacitance and adapted to sink the second current based on the charge stored by the reservoir capacitance and the bias voltage, and a third terminal adapted to provide the second current.

5. The voltage regulator of claim 4 wherein the current mirror provides the fourth current to the second terminal of the output transistor and the first current is provided to the reservoir capacitance from the second terminal of the output transistor based on a difference between the fourth current and the second current.

6. The voltage regulator of claim 4 when a portion of the charge is drawn from the reservoir capacitance by a load, a voltage differential between the first and second terminals of the output transistor decreases and the output transistor operates to reduce the second current based on the reduced voltage differential, thereby increasing the first current and restoring the portion of the charge to the reservoir capacitance.

7. The voltage regulator of claim 1 wherein the second circuitry comprises:

a first current source adapted to sink a fifth current, wherein the fifth current is a constant current; and

a second current source adapted to sink the third current from the current mirror based on the second current such that a sum of the second current and the third current is essentially equal to the constant current.

8. The voltage regulator of claim 1 wherein when a portion of the charge is drawn from the reservoir capacitance by a load, the first circuitry operates to reduce the second current.

9. The voltage regulator of claim 8 wherein when the second current decreases, the second circuitry operates to increase the third current such that the sum of the second and third currents is essentially equal to a constant current.

10. The voltage regulator of claim 9 wherein when the third current increases, the current mirror further operates to increase the fourth current to reflect the increase in the third current.

11. The voltage regulator of claim 10 wherein the fourth current is defined as the third current multiplied by the current mirror gain ratio.

12. The voltage regulator of claim 1 wherein the reservoir capacitance, first circuitry, second circuitry, and the current mirror are fabricated on a single semiconductor die.

13. The voltage regulator of claim 4 further comprising voltage bias circuitry adapted to receive a stable reference voltage and provide the DC bias to the output transistor.

14. The voltage regulator of claim 13 wherein the voltage bias circuitry comprises an amplifier adapted to amplify the stable reference voltage to provide the DC bias.

15. The voltage regulator of claim 14 wherein the voltage bias circuitry further comprises an output matching transistor in a feedback loop of the amplifier, wherein the output matching transistor compensates for a differential voltage between the first and second terminals of the output transistor.

16. A method for regulating an output voltage of a voltage regulator comprising:

storing charge in a reservoir capacitance corresponding to a regulated output voltage, wherein the charge stored is controlled by a first current;

providing a second current based on the charge stored by the reservoir capacitance;

generating a third current that is inversely related to the second current;

providing a fourth current based on the third current and a gain ratio; and

providing the first current based on the fourth current such that the charge stored by the reservoir capacitance increases when the fourth current increases.

17. The method of claim 16 wherein the first current is substantially equal to a difference between the fourth current and the second current.

18. The method of claim 16 wherein the step of generating the third current comprises:

generating a fifth current, wherein the fifth current is a constant current; and

generating the third current based on the second current such that a sum of the second current and the third current is essentially equal to the constant current.

19. The method of claim 16 wherein when a portion of the charge is drawn from reservoir capacitance by a load, the step of providing the second current further comprises reducing the second current to reflect the portion of the charge drawn from the reservoir capacitance.

20. The method of claim 19 wherein when the second current decreases, the step of generating the third current comprises increasing the third current such that the sum of the second and third currents is essentially equal to the constant current.

21. The method of claim 20 wherein when the third current increases, the step of providing the fourth current comprises increasing the fourth current to reflect the increase in the third current.

22. The method of claim 21 wherein the fourth current is defined as the third current multiplied by the gain ratio.

23. The method of claim 16 further comprising providing a DC bias based on a stable reference voltage, wherein the step of providing the second current is further based on the DC bias.

24. The method of claim 23 wherein the step of providing the DC bias comprises amplifying the stable reference voltage to provide the DC bias.

25. A system comprising:

a voltage regulator comprising a reservoir capacitance and adapted to control charge stored by the reservoir capacitance such that the charge corresponds to a regulated output voltage;

a reconstruction filter adapted to receive a digital signal from a data interface, sample the regulated output voltage based on the digital signal during a sampling phase of the reconstruction filter to generate a sampling signal, and provide an output signal based on the sampling signal;

first charge compensation circuitry adapted to supply charge to the reservoir capacitance during the sampling phase of the reconstruction filter; and

second charge compensation circuitry adapted to supply charge to the reservoir capacitance when the digital signal transitions between a first logic state and a second logic state.

26. The system of claim 25 wherein the first charge compensation circuitry comprises:

a compensation capacitor adapted to store charge provided by a supply voltage; and

circuitry adapted to couple the compensation capacitor to the reservoir capacitance during the sampling phase of the reconstruction filter, thereby providing the charge stored by the compensation capacitor to the reservoir capacitance.

27. The system of claim 26 wherein the reconstruction filter and the first compensation circuitry are further adapted to receive a first and second non-overlapping clock signal and the sampling phase of the reconstruction filter is when the first non-overlapping clock signal is asserted.

28. The system of claim 27 wherein the circuitry is further adapted to couple the compensation capacitor to the supply voltage when the first non-overlapping clock signal is not asserted such that charge is supplied from the supply voltage to the compensation capacitor.

29. The system of claim 26 wherein the compensation capacitor is sized such that the compensation capacitor provides essentially the same amount of charge to the reservoir capacitance as taken from the reservoir capacitance by the reconstruction filter during the sampling phase.

30. The system of claim 26 the second charge compensation circuitry comprises:

a second compensation capacitor adapted to store charge provided by the supply voltage;

a third compensation capacitor adapted to store charge provided by the supply voltage;

second circuitry adapted to couple the second compensation capacitor to the reservoir capacitance when the digital signal transitions from the first logic state to the second logic state, thereby providing the charge stored by the second compensation capacitor to the reservoir capacitance; and

third circuitry adapted to couple the third compensation capacitor to the reservoir capacitance when the digital signal transitions from the second logic state to the first logic state, thereby providing the charge stored by the third compensation capacitor to the reservoir capacitance.

31. The system of claim 30 wherein the digital signal is a differential signal having a first differential component and a second differential component and the second circuitry operates based on the first differential component and the third circuitry operates based on the second differential component.

32. The system of claim 30 wherein the second circuitry is further adapted to couple the second compensation capacitor to the supply voltage when the digital signal transitions from the second logic state to the first logic state and the third circuitry is further adapted to couple the third compensation capacitor to the supply voltage when the digital signal transitions from the first logic state to the second logic state.

33. The system of claim 30 wherein the second compensation capacitor is sized such that the second compensation capacitor provides essentially the same amount of charge to the reservoir capacitance as taken from the reservoir capacitance by the data interface when the data signal transitions from the first logic state to the second logic state.

34. The system of claim 33 wherein the third compensation capacitor is sized such that the third compensation capacitor provides essentially the same amount of charge to the reservoir capacitance as taken from the reservoir capacitance by the data interface when the data signal transitions from the second logic state to the first logic state.

35. The system of claim 34 wherein the second and third compensation capacitors are further sized to essentially match a gate capacitance of the data interface.

36. The system of claim 32 further comprising a second voltage regulator adapted to provide the supply voltage such that the regulated output voltage is isolated from voltage drops in the supply voltage due to operation of the first and second charge compensation circuitries.

37. The system of claim 25 wherein the first charge compensation circuitry has an RC time constant that is essentially the same as an RC time constant of sampling circuitry in the reconstruction filter.

38. The system of claim 25 wherein the voltage regulator wherein the charge stored by the reservoir capacitance is controlled by a first current and the voltage regulator further comprises:

first circuitry adapted to provide a second current based on the charge stored by the reservoir capacitance;

second circuitry adapted to receive the second current and generate a third current that is inversely related to the second current; and

a current mirror adapted to provide a fourth current based on the third current and a current mirror gain ratio;

the first circuitry further adapted to provide the first current based on the fourth current such that the charge stored by the reservoir capacitance increases when the fourth current increases.

39. The system of claim 38 wherein the first current is related to a difference between the fourth current and the second current.

40. The system of claim 38 wherein the first current is substantially equal to a difference between the fourth current and the second current.

41. The system of claim 38 wherein the first circuitry comprises an output transistor having an input terminal adapted to receive a bias voltage, a second terminal coupled to the reservoir capacitance and adapted to sink the second current based on the charge stored by the reservoir capacitance and the bias voltage, and a third terminal adapted to provide the second current.

42. The system of claim 41 wherein the current mirror provides the fourth current to the second terminal of the output transistor and the first current is provided to the reservoir capacitance from the second terminal of the output transistor based on a difference between the fourth current and the second current.

43. The system of claim 41 when a portion of the charge is drawn from the reservoir capacitance by a load, a voltage differential between the first and second terminals of the output transistor decreases and the output transistor operates to reduce the second current based on the reduced voltage differential, thereby increasing the first current and restoring the portion of the charge to the reservoir capacitance.

44. The system of claim 38 wherein the second circuitry comprises:

a first current source adapted to sink a fifth current, wherein the fifth current is a constant current; and

a second current source adapted to sink the third current from the current mirror based on the second current such that a sum of the second current and the third current is essentially equal to the constant current.

45. The system of claim 38 wherein when a portion of the charge is drawn from the reservoir capacitance by a load, the first circuitry operates to reduce the second current.

46. The system of claim 45 wherein when the second current decreases, the second circuitry operates to increase the third current such that the sum of the second and third currents is essentially equal to a constant current.

47. The system of claim 46 wherein when the third current increases, the current mirror further operates to increase the fourth current to reflect the increase in the third current.

48. The system of claim 47 wherein the fourth current is defined as the third current multiplied by the current mirror gain ratio.

49. The system of claim 38 wherein the reservoir capacitance, first circuitry, second circuitry, and the current mirror are fabricated on a single semiconductor die.

50. The system of claim 41 further comprising voltage bias circuitry adapted to receive a stable reference voltage and provide the DC bias to the output transistor.

51. The system of claim 50 wherein the voltage bias circuitry comprises an amplifier adapted to amplify the stable reference voltage to provide the DC bias.

52. The system of claim 51 wherein the voltage bias circuitry further comprises an output matching transistor in a feedback loop of the amplifier, wherein the output matching transistor compensates for a differential voltage between the first and second terminals of the output transistor.