Circuit and method for a switch matrix and switch sensing

• US 7,151,432 B2
• Filed: 09/19/2001
• Issued: 12/19/2006
• Est. Priority Date: 09/19/2001
• Status: Expired due to Term

• Current Assignee: Immersion Corporation
• Original Assignee: Immersion Corporation
• Inventors: Tierling, Kollin
• Primary Examiner(s): Zimmerman, Brian
• Assistant Examiner(s): NGUYEN, NAM V
• Application Number:
  US09/957,004
• Publication Number:
  US 20030058845A1
• Time in Patent Office: 1,917 Days
• Field of Search: 340 144- 146, 340/2.8, 340/2.9, 340/2.7, 340/14.61, 340 1462- 1469, 341/22, 341/26, 341/20, 341/24, 341/25
• US Class Current: 340/2.28
• CPC Class Codes: H03M 11/20 Dynamic coding, i.e. by key scanning H03M11/26 takes precedence

Abstract

Aspects of a switch matrix circuit are provided. In accordance with a circuit aspect, a plurality of switches are organized in a row and column configuration. Coupled to the plurality of switches is a current sensing circuit. The current sensing circuit includes a transistor and at least one resistor per column of the plurality of switches. Current amplified by the transistor and converted by the at least one resistor in a column is sensed as a logic level indicative of a switch status within the column for a selected row. The current sensing arrangement may also be used in an embodiment utilizing bi-directional signal control to minimize the number of I/O lines required to scan the switch matrix. The bi-directional signal scanning may also be implemented in another embodiment that senses voltage levels to determine switch closures.

Claims

1. A switch matrix circuit comprising:

a plurality of switches organized in a row and column configuration; and

a current sensing circuit coupled to the plurality of switches, the current sensing circuit including a transistor per column of the plurality of switches, and a plurality of resistors each electrically coupled in series with an associated one of the plurality of switches, wherein current amplified by the transistor in a column is sensed as a logic state indicative of a switch status of a switch within the column for a selected row, and wherein the column is configured to conduct at least a threshold current level required for the transistor to perform the amplification if the switch is closed, and to conduct less than the threshold current level if the switch is open, regardless of how many other of the plurality of switches are closed.

2. The switch matrix circuit of claim 1, wherein the transistor comprises a bipolar junction transistor.

3. The switch matrix circuit of claim 1, wherein the row and column configuration further comprises an off-diagonal configuration having one switch per row and column intersection in all but one intersection per row.

4. The switch matrix circuit of claim 3, wherein each intersection lacking a switch lies in a different column within each row.

5. The switch matrix circuit of claim 4, wherein a single scan line supports providing a row input signal or reading a column output signal for one row and one column within the off-diagonal configuration.

6. The switch matrix circuit of claim 1, wherein a processor is configured to sense the switch status.

7. A circuit for more efficient switch selection sensing, the circuit comprising:

a switch matrix comprising a plurality of switches organized as a plurality of rows and columns;

a current sensing circuit coupled to the switch matrix; and

a processor coupled to the switch matrix and the current sensing circuit by a plurality of scan lines, wherein selection of a single row by a scan line returns column current levels from the current sensing circuit to detect if a switch at an intersection of the single row and a column of the switch matrix is closed, and wherein a column current level associated with the column is at least a threshold current level required for detection if the switch is closed, and the column current level associated with the column is less than the threshold current level if the switch is open, regardless of how many other of the plurality of switches are closed.

8. The circuit of claim 7, wherein the plurality of scan lines further comprises a plurality of bi-directional scan lines, wherein each scan line provides both row selection and column sensing capabilities.

9. The circuit of claim 8, wherein the organization of the plurality of switches further comprise an off-diagonal organization to support the bi-directional scan lines.

10. The circuit of claim 7, wherein the current sensing circuit further comprises a circuit comprising a plurality of transistors each coupled to an associated column, and a plurality of resistors each coupled in series with an associated one of the plurality of switches in the switch matrix.

11. The circuit of claim 10, wherein the column current level associated with the column is at least the threshold current level when the transistor coupled to the column is turned on.

12. The circuit of claim 10, wherein the transistor comprises a bipolar junction transistor.

13. A method for sensing switch statuses, the method comprising:

coupling a current sensing circuit to a switch matrix having a plurality of switches in a row and column configuration comprising one switch per row and column intersection;

amplifying a current signal; and

detecting a switch status of a switch within the switch matrix based on whether a current signal in the current sensing circuit comprises at least a threshold current level, regardless of how many other of the plurality of switches are closed.

14. The method of claim 13, further comprising forming the current sensing circuit comprising a transistor per column of the plurality of switches and a plurality of resistors each electrically coupled in series with an associated one of the plurality of switches.

15. The method of claim 14, wherein detecting the switch status of the switch further comprises detecting current amplified by the transistor in a column as a logic state indicative of the switch status of the switch, wherein the switch is located at an intersection of the column and a selected row.

16. The method of claim 14, wherein the transistor per column of the plurality of switches comprises a bipolar junction transistor.

17. The method of claim 13, wherein the switch matrix further comprises a plurality of bi-directional scan lines, wherein each bi-directional scan line provides both row selection and column sensing capabilities.

18. The method of claim 17, wherein the plurality of switches comprises an off-diagonal organization to support the bi-directional scan lines.

19. The method of claim 13, wherein the row and column configuration comprises a first row and a second row, and wherein detecting the switch status comprises:

scanning the first row of the switch matrix; and

then

scanning the second row of the switch matrix.

24. The method of claim 13, wherein detecting the switch status of the switch comprises:

receiving a base current level associated with a low logic state in a selected row of the switch matrix, wherein the switch is located at the intersection of the selected row and a column;

if the switch is closed, amplifying at least a portion of the base current level conducted by the column to at least the threshold current level with a transistor coupled at its base to the column and at its emitter to a scan line; and

scanning the scan line for the current signal, wherein the switch status is open if the current signal is less than the threshold current level, and wherein the switch status is closed if the current signal is at least the threshold current level.

25. The method of claim 24, wherein the selected row is a first selected row, and further comprising:

before receiving the base current level in the first selected row, selecting the first selected row from a selectable plurality of rows in the switch matrix;

discontinuing to receive the base current level in the first selected row;

selecting a second row from the plurality of selectable rows; and

receiving the base current level in the second row.

20. A switch matrix circuit comprising:

a plurality of switches organized in a row and column off-diagonal configuration having one switch per row and column intersection in all but one intersection per row; and

a plurality of bi-directional scan lines, wherein a single bi-directional scan line provides both row selection and column sensing capabilities for switch status identification, wherein;

a first bi-directional scan line of the plurality of bi-directional scan lines is configured to conduct a first signal associated with a first logic state to a selected row of the switch matrix coupled thereto;

a second bi-directional scan line of the plurality of bi-directional scan lines is configured to be scanned for an output signal comprising at least a threshold level, wherein the output signal comprises at least the threshold level only if a scanned switch at an intersection of the selected row and a scanned column of the switch matrix is selected, wherein the scanned column is coupled to the second bi-directional scan line; and

each of the other bi-directional scan lines of the plurality of bi-directional scan lines is configured to conduct a second signal associated with a second logic state opposite the first logic state.

21. The switch matrix of claim 20, wherein the one intersection per row lacking a switch lies in a different column within each row.

22. The switch matrix of claim 20, wherein an analog to digital converter is configured to sense switch status for the scanned switch, wherein a closed switch status is sensed if the output signal comprises at least the threshold level, and an open switch status is sensed if the output signal comprises less than the threshold level.

23. The switch matrix of claim 20, further comprising a diode and resistor circuit for each scan line.