Semiconductor memory device including global IO line with low-amplitude driving voltage signal applied thereto

• US 7,151,703 B2
• Filed: 11/03/2004
• Issued: 12/19/2006
• Est. Priority Date: 04/12/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Joo, Yong-suk, Lee, Geun-il
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US10/980,663
• Publication Number:
  US 20050226060A1
• Time in Patent Office: 776 Days
• Field of Search: 365/189.11, 365/227, 365/185.23
• US Class Current: 365/189.11
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

A semiconductor memory device including a global IO line with a low-amplitude driving voltage signal applied thereto. In the device, a first driver converts a data signal of a first voltage level from a memory cell to a second voltage level in response to a read control signal, and outputs it to a global IO line. A first level shifter converts the data signal of the second voltage level from the line back to the first voltage level, and outputs it to a data output terminal. A second driver converts an external data signal of a first voltage level from a data input terminal to a second voltage level, and outputs it to a global IO line. A second level shifter converts the external data signal of the second voltage level from the line back to the first voltage level and outputs it to a write driver.

Claims

1. A semiconductor memory device including a global input/output line with a low-amplitude driving voltage signal applied thereto, the device comprising:

a driver for driving a cell data having a first voltage level by a sense amplifier to a second voltage level and outputting the data to the global input/output line in response to a read control signal; and

a level shifter for converting the data signal of the second voltage level transmitted through the global input/output line to the first voltage level and then outputting to a data output terminal.

2. The device according to claim 1, wherein the second voltage level is lower than the first voltage level.

3. The device according to claim 1, wherein the driver includes:

a pull-up means for bringing the global IO line to the second level in response to a control signal obtained by a logical operation between the read control signal and the data signal; and

a pull-down means for bringing the global IO line to a ground voltage level in response to a control signal obtained by a logical operation between the read control signal and an inverted signal of the data signal.

4. The device according to claim 3, wherein the driver further includes a delay unit for controlling data skew between the data signal and the inverted signal due to an increase and a decrease in respective signal levels of the data signal and the inverted signal.

5. The device according to claim 1, wherein the level shifter includes a switching element for activating or deactivating the level shifter in response to the read control signal.

6. A semiconductor memory device including the global IO line with a low-amplitude driving voltage signal applied thereto, the device comprising:

a driver for converting an external data signal of a first voltage level received from a data input terminal to a second voltage level and outputting the external data signal of the second voltage level to a global IO line according to a write control signal; and

a level shifter for converting the external data signal of the second voltage level received via the global IO line to the first voltage level and outputting the external data signal of the first voltage level to a write driver.

7. The device according to claim 6, wherein the second voltage level is lower than the first voltage level.

8. The device according to claim 6, wherein the driver includes:

a pull-up means for bringing the global IO line to the second level in response to a control signal obtained by a logical operation between the write control signal and the external data signal; and

a pull-down means for bringing the global IO line to a ground voltage level in response to a control signal obtained by a logical operation between the write control signal and an inverted signal of the external data signal.

9. The device according to claim 8, wherein the driver further includes a delay unit for controlling data skew between the external data signal and the inverted signal due to an increase and a decrease in respective signal levels of the external data signal and the inverted signal.

10. The device according to claim 6, wherein the level shifter includes a switching element for activating or deactivating the level shifter in response to the write control signal.

11. A semiconductor memory device including a global IO line with a low-amplitude driving voltage signal applied thereto, the device comprising:

a first driver for converting a cell data signal, received from a memory cell after being amplified to a first voltage level by a sense amplifier, to a second voltage level in response to a read control signal and then outputting the cell data signal of the second voltage level to the global IO line;

a first level shifter for converting the cell data signal of the second voltage level received via the global IO line to the first voltage level and then outputting the cell data signal of the first voltage level to a data output terminal;

a second driver for converting an external data signal of the first voltage level received from a data input terminal to the second voltage level and outputting the external data signal of the second voltage level to the global IO line; and

a second level shifter for converting the external data signal of the second voltage level received via the global IO line to the first voltage level and outputting the external data signal of the first voltage level to a write driver.

12. The device according to claim 11, wherein the second voltage level is lower than the first voltage level.

13. The device according to claim 11, wherein the first driver includes:

a first pull-up means for bringing the global IO line to the second voltage level in response to a control signal obtained by a logical operation between the read control signal and the cell data signal; and

a first pull-down means for bringing the global IO line to a ground voltage level in response to a control signal obtained by a logical operation between the read control signal and an inverted signal of the cell data signal, and

wherein the second driver includes;

a second pull-up means for bringing the global IO line to the second voltage level in response to a control signal obtained by a logical operation between the write control signal and the external data signal; and

a second pull-down means for bringing the global IO line to the ground voltage level in response to a control signal obtained by a logical operation between the write control signal and an inverted signal of the external data signal.

14. The device according to claim 13, wherein the first driver further includes a first delay unit for controlling data skew between the cell data signal and the inverted signal thereof due to an increase and a decrease in respective signal levels of the cell data signal and the inverted signal thereof, and

wherein the second driver further includes a second delay unit for controlling data skew between the external data signal and the inverted signal thereof due to an increase and a decrease in respective signal levels of the external data signal and the inverted signal thereof.

15. The device according to claim 11, wherein the first level shifter includes a first switching element for activating or deactivating the first level shifter in response to the read control signal, and

wherein the second level shifter includes a second switching element for activating or deactivating the second level shifter in response to the write control signal.

16. The device according to claim 11, wherein the second voltage level is lower than the first voltage level,

wherein the first driver includes:

a first pull-up means for bringing the global IO line to the second voltage level in response to a control signal obtained by a logical operation between the read control signal and the cell data signal;

a first pull-down means for bringing the global IO line to a ground voltage level in response to a control signal obtained by a logical operation between the read control signal and an inverted signal of the cell data signal; and

a first delay unit for controlling data skew between the cell data signal and the inverted signal thereof due to an increase and a decrease in respective signal levels of the cell data signal and the inverted signal thereof, and

wherein the first level shifter includes a first switching element for activating or deactivating the first level shifter in response to the read control signal.

17. The device according to claim 11, wherein the second voltage level is lower than the first voltage level,

wherein the second driver includes:

a second pull-up means for bringing the global IO line to the second voltage level in response to a control signal obtained by a logical operation between the write control signal and the external data signal;

a second pull-down means for bringing the global IO line to a ground voltage level in response to a control signal obtained by a logical operation between the write control signal and an inverted signal of the external data signal; and

a second delay unit for controlling data skew between the external data signal and the inverted signal thereof due to an increase and a decrease in respective signal levels of the external data signal and the inverted signal thereof, and

wherein the second level shifter includes a second switching element for activating or deactivating the second level shifter in response to the write control signal.