Reconfigurable test system

• US 7,152,027 B2
• Filed: 10/19/2001
• Issued: 12/19/2006
• Est. Priority Date: 02/17/1998
• Status: Expired due to Term

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Ryan, Arthur, Odom, Brian Keith, Andrade, Hugo A.
• Primary Examiner(s): Rodriguez, Paul
• Assistant Examiner(s): OSBORNE, LUKE R
• Application Number:
  US10/034,565
• Publication Number:
  US 20020055834A1
• Time in Patent Office: 1,887 Days
• Field of Search: 703/21, 703/23
• US Class Current: 703/21
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A reconfigurable test system including a host computer coupled to a reconfigurable test instrument. The reconfigurable test instrument includes reconfigurable hardware—i.e. a reconfigurable hardware module with one or more programmable elements such as Field Programmable Gate Arrays for realizing an arbitrary hardware architecture and a reconfigurable front end with programmable transceivers for interfacing with any desired physical medium—and optionally, an embedded processor. A user specifies system features with a software configuration utility which directs a component selector to select a set of software modules and hardware configuration files from a series of libraries. The modules are embedded in a host software driver or downloaded for execution on the embedded CPU. The configuration files are downloaded to the reconfigurable hardware. The entire selection process is performed in real-time and can be changed whenever the user deems necessary. Alternatively, the user may create a graphical program in a graphical programming environment and compile the program into various software modules and configuration files for host execution, embedded processor execution, or programming the reconfigurable hardware.

Claims

1. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, wherein the device also includes one or more programmable transceivers coupled to the programmable hardware element, the method comprising:

creating a block diagram in response to user input, wherein the block diagram specifies at least a portion of the measurement function;

generating a hardware architecture file based on at least a portion of the block diagram, wherein the hardware architecture file describes a hardware implementation of the at least a portion of the block diagram;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the one or more programmable transceivers in the device;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element and the one or more programmable transceivers in the device executing to perform the measurement function on the signal.

2. The method of claim 1,

wherein said configuring the one or more programmable transceivers comprises configuring the one or more programmable transceivers utilizing the hardware architecture file.

3. The method of claim 1, further comprising:

creating a programmable transceiver configuration file which describes a configuration for the one or more programmable transceivers;

wherein said configuring the one or more programmable transceivers comprises configuring the one or more programmable transceivers utilizing the programmable transceiver configuration file.

4. The method of claim 1,

wherein the block diagram includes a first portion that specifies a configuration for the programmable hardware element, and wherein the block diagram includes a second portion that specifies a configuration for the one or more programmable transceivers;

wherein said generating comprises generating the hardware architecture file based on the first portion of the block diagram; and

wherein said configuring the one or more programmable transceivers comprises configuring the one or more programmable transceivers based on the second portion of the block diagram.

5. The method of claim 1,

wherein the block diagram includes a first portion that specifies a configuration for the programmable hardware element, and wherein the block diagram includes a second portion that specifies a configuration for the one or more programmable transceivers;

wherein said generating comprises generating the hardware architecture file based on the first portion of the block diagram;

the method further comprising creating a programmable transceiver configuration file based on the second portion of the block diagram, wherein the programmable transceiver configuration file describes a configuration for the one or more programmable transceivers;

wherein said configuring the one or more programmable transceivers comprises configuring the one or more programmable transceivers utilizing the programmable transceiver configuration file.

6. The method of claim 1, further comprising:

creating a second block diagram in response to user input, wherein the second block diagram specifies at least a portion of the measurement function;

creating a programmable transceiver configuration file based on the second block diagram, wherein the programmable transceiver configuration file describes a configuration for the one or more programmable transceivers;

wherein said configuring the one or more programmable transceivers comprises configuring the one or more programmable transceivers utilizing the programmable transceiver configuration file.

7. The method of claim 1, wherein the device also includes a processor and memory coupled to the programmable hardware element;

the method further comprising;

storing an executable program in the memory of the device for execution by the processor on the device, wherein the executable program operates with the programmable hardware element and the one or more programmable transceivers to perform the measurement function.

8. The method of claim 1, wherein the device also includes a processor and memory coupled to the programmable hardware element;

wherein the hardware architecture file is based on a first portion of the block diagram;

the method further comprising;

generating an executable program based on a second portion of the block diagram;

storing the executable program in the memory of the device for execution by the processor on the device.

9. The method of claim 1, wherein the device is coupled to a computer system;

wherein said creating, said generating, and said configuring are performed in response to software executing on the computer system.

10. The method of claim 1, wherein the block diagram comprises a graphical program.

11. The method of claim 1, wherein the block diagram comprises a portion of a graphical program, wherein the graphical program also includes a display portion.

12. The method of claim 1, further comprising:

displaying one or more panels on a display during the programmable hardware element in the device executing to perform the measurement function on the signal, wherein at least one of the one or more panels displays the measured signal.

13. The method of claim 12,

wherein said displaying one or more panels comprises at least one of the one or more panels displaying output from the device during said executing.

14. The method of claim 12, further comprising:

receiving user input to at least one of the one or more panels during said executing;

providing the user input to the programmable hardware element; and

the programmable hardware element adjusting the measurement function on the signal in response to the user input.

15. The method of claim 12,

wherein the one or more panels comprise a user interface useable for viewing data generated by the device during the programmable hardware element in the device executing to perform the measurement function on the signal.

16. The method of claim 12,

wherein the one or more panels comprise a user interface useable for controlling the device and viewing output data from the device during the programmable hardware element in the device executing to perform the measurement function on the signal;

the method further comprising;

receiving user input to at least one of the one or more panels on the display to control the device during the programmable hardware element in the device executing to perform the measurement function on the signal.

17. The method of claim 12,

wherein the device is coupled to a computer system, wherein the computer system includes the display;

wherein said displaying comprises the computer system executing software to display the one or more panels on the display during the programmable hardware element in the device executing to perform the measurement function on the signal.

18. The method of claim 17,

wherein the block diagram comprises a portion of a graphical program, wherein the graphical program also includes a display portion;

wherein the display portion of the graphical program specifies the one or more panels;

the method further comprising;

compiling a portion of the graphical program corresponding to the one or more panels into executable code for execution by the computer system.

19. The method of claim 1,

wherein the device operates as an instrument;

wherein the external source is a unit under test.

20. The method of claim 19, further comprising:

at least one of the programmable hardware element and the one or more programmable transceivers generating a stimulus signal to the unit under test prior to the device acquiring the signal from unit under test.

21. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, wherein the device also includes one or more programmable transceivers coupled to the programmable hardware element, the method comprising:

creating a first block diagram, wherein the first block diagram specifies a first portion of the measurement function;

creating a second block diagram, wherein the second block diagram specifies a second portion of the measurement function;

generating a hardware architecture file based on the first portion of the block diagram, wherein the hardware architecture file describes a hardware implementation of the first portion of the block diagram;

generating a programmable transceiver configuration file based on the second portion of the block diagram, wherein the programmable transceiver configuration file describes a configuration for the one or more programmable transceivers;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the one or more programmable transceivers in the device utilizing the programmable transceiver configuration file;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element and the one or more programmable transceivers in the device executing to perform the measurement function on the signal.

22. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, wherein the device also includes one or more programmable transceivers coupled to the programmable hardware element, the method comprising:

creating a block diagram, wherein the block diagram specifies the measurement function;

generating configuration information based on at least a portion of the block diagram, wherein the configuration information describes a hardware implementation of the at least a portion of the block diagram;

configuring the programmable hardware element and the one or more programmable transceivers in the device utilizing the configuration information, wherein after said configuring the programmable hardware element and the one or more programmable transceivers implement a hardware implementation of the at least a portion of the block diagram;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element and the one or more programmable transceivers in the device executing to perform the measurement function on the signal.

23. The method of claim 22,

wherein the configuration information includes a hardware architecture file;

wherein said configuring comprises configuring the programmable hardware element using the hardware architecture file.

24. The method of claim 22,

wherein the configuration information includes a programmable transceiver configuration file;

wherein said configuring comprises configuring the one or more programmable transceivers using the programmable transceiver configuration file.

25. The method of claim 22,

wherein the configuration information includes a hardware architecture file and a programmable transceiver configuration file;

wherein said configuring comprises configuring the programmable hardware element using the hardware architecture file and configuring the one or more programmable transceivers using the programmable transceiver configuration file.

26. A reconfigurable measurement system, comprising:

a computer system comprising a processor, memory and a display;

wherein the memory stores a block diagram, wherein the block diagram implements a measurement function;

wherein the memory also stores a software program which is executable to generate configuration information based on the block diagram, wherein the configuration information describes a hardware implementation of the block diagram; and

a device coupled to the computer system, wherein the device includes;

an input for acquiring a signal from an external source;

a programmable hardware element, wherein the programmable hardware element in the device is configurable utilizing the configuration information; and

one or more programmable transceivers coupled to the programmable hardware element, wherein the one or more programmable transceivers in the device are configurable utilizing the configuration information;

wherein after being configured the programmable hardware element and the one or more programmable transceivers implement a hardware implementation of the block diagram;

wherein the programmable hardware element and the one or more programmable transceivers are operable to perform the measurement function on an acquired signal.

27. The reconfigurable measurement system of claim 26,

wherein the configuration information includes a hardware architecture file;

wherein the programmable hardware element is operable to be configured using the hardware architecture file.

28. The reconfigurable measurement system of claim 26,

wherein the configuration information includes a programmable transceiver configuration file;

wherein the one or more programmable transceivers are operable to be configured using the programmable transceiver configuration file.

29. The reconfigurable measurement system of claim 26,

wherein the configuration information includes a hardware architecture file and a programmable transceiver configuration file;

wherein the programmable hardware element is operable to be configured using the hardware architecture file, and wherein the one or more programmable transceivers are operable to be configured using the programmable transceiver configuration file.

30. The reconfigurable measurement system of claim 26,

wherein the block diagram includes a first portion that specifies a configuration for the programmable hardware element, and wherein the block diagram includes a second portion that specifies a configuration for the one or more programmable transceivers;

wherein the configuration information includes a hardware architecture file and a programmable transceiver configuration file;

wherein the software program is executable to generate the hardware architecture file based on the first portion of the block diagram; and

wherein the software program is executable to generate the programmable transceiver configuration file based on the second portion of the block diagram.

31. The reconfigurable measurement system of claim 26,

wherein the device also includes a processor and memory coupled to the programmable hardware element;

wherein the memory of the devices stores an executable program for execution by the processor on the device, wherein the executable program operates with the programmable hardware element and the one or more programmable transceivers to perform the measurement function.

32. The reconfigurable measurement system of claim 31,

wherein the software program is executable to generate the executable program based on the block diagram.

33. The reconfigurable measurement system of claim 26, wherein the block diagram comprises a graphical program.

34. The reconfigurable measurement system of claim 26, wherein the block diagram comprises a portion of a graphical program, wherein the graphical program also includes a display portion.

35. The reconfigurable measurement system of claim 26,

wherein the computer system is operable to display one or more panels on the display while the programmable hardware element and the one or more programmable transceivers in the device execute to perform the measurement function on the signal, wherein at least one of the one or more panels displays the measured signal.

36. The reconfigurable measurement system of claim 26,

wherein the software program is executable to select pre-existing configuration information based on the block diagram.

37. The reconfigurable measurement system of claim 26,

wherein the device operates as an instrument;

wherein the external source is a unit under test.

38. The reconfigurable measurement system of claim 37, wherein the device is operable to be coupled to a unit under test (UUT) in order to test the UUT;

wherein different types of UUTs may be coupled to the device;

wherein the device is reconfigurable to test the different types of UUTs.

39. The reconfigurable measurement system of claim 37,

wherein different types of UUTs having various testing requirements may be coupled to the device;

wherein the reconfigurable measurement system is reconfigurable to test said different types of UUTs having said various testing requirements.

40. The reconfigurable measurement system of claim 26,

wherein the programmable hardware element comprises a Field Programmable Gate Array (FPGA).

41. The reconfigurable measurement system of claim 26,

wherein the memory of the computer system stores a graphical design environment for creating the block diagram.

42. The reconfigurable measurement system of claim 26,

wherein the block diagram comprises at least a portion of a graphical program;

wherein the memory of the computer system stores a graphical programming development environment for creating the block diagram.

43. The reconfigurable measurement system of claim 26,

wherein the block diagram comprises a data flow block diagram;

wherein the memory of the computer system stores a graphical data flow programming development environment for creating the data flow block diagram.

44. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, wherein the device also includes one or more programmable transceivers coupled to the programmable hardware element, the method comprising:

creating a block diagram in response to user input, wherein the block diagram specifies at least a portion of the measurement function;

receiving user input specifying a first portion of the block diagram to be implemented in the programmable hardware element and a second portion of the block diagram to be implemented by the one or more programmable transceivers;

generating a hardware architecture file based on the first portion of the block diagram, wherein the hardware architecture file describes a hardware implementation of the first portion of the block diagram;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the one or more programmable transceivers in the device based on the second portion of the block diagram;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element and the one or more programmable transceivers in the device executing to perform the measurement function on the signal.

45. The method of claim 44, the method further comprising:

creating a programmable transceiver configuration file based on the second portion of the block diagram, wherein the programmable transceiver configuration file describes a configuration for the one or more programmable transceivers.

wherein said configuring the one or more programmable transceivers comprises configuring the one or more programmable transceivers utilizing the programmable transceiver configuration file.

46. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, wherein the device also includes one or more programmable transceivers coupled to the programmable hardware element, the method comprising:

creating a first block diagram in response to user input, wherein the first block diagram specifies a first portion of the measurement function;

creating a second block diagram in response to user input, wherein the second block diagram specifies a second portion of the measurement function;

receiving user input specifying the first block diagram to be implemented in the programmable hardware element and the second block diagram to be implemented by the one or more programmable transceivers;

generating a hardware architecture file based on the first block diagram, wherein the hardware architecture file describes a hardware implementation of the first block diagram;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the one or more programmable transceivers in the device based on the second block diagram;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element and the one or more programmable transceivers in the device executing to perform the measurement function on the signal.

47. The method of claim 46, wherein the second block diagram is a sub-diagram of the first block diagram.

48. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, wherein the device also includes programmable switching circuitry coupled to the programmable hardware element, the method comprising:

creating a block diagram in response to user input, wherein the block diagram specifies at least a portion of the measurement function;

generating a hardware architecture file based on at least a portion of the block diagram, wherein the hardware architecture file describes a hardware implementation of the at least a portion of the block diagram;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the programmable switching circuitry in the device;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element and the programmable switching circuitry in the device executing to perform the measurement function on the signal.

49. The method of claim 48,

wherein said configuring the programmable switching circuitry comprises configuring the programmable switching circuitry utilizing the hardware architecture file.

50. The method of claim 48, further comprising:

creating a programmable switching circuitry configuration file which describes a configuration for the programmable switching circuitry;

wherein said configuring the programmable switching circuitry comprises configuring the programmable switching circuitry utilizing the programmable switching circuitry configuration file.

51. The method of claim 48,

wherein the block diagram includes a first portion that specifies a configuration for the programmable hardware element, and wherein the block diagram includes a second portion that specifies a configuration for the programmable switching circuitry;

wherein said generating comprises generating the hardware architecture file based on the first portion of the block diagram; and

wherein said configuring the programmable switching circuitry comprises configuring the programmable switching circuitry based on the second portion of the block diagram.

52. The method of claim 48, wherein the device also includes a processor and memory coupled to the programmable hardware element;

the method further comprising;

storing an executable program in the memory of the device for execution by the processor on the device, wherein the executable program operates with the programmable hardware element and the programmable switching circuitry to perform the measurement function.

53. The method of claim 48, wherein the block diagram comprises a graphical program.

54. A reconfigurable measurement system, comprising:

a computer system comprising a processor, memory and a display;

wherein the memory stores a block diagram, wherein the block diagram implements a measurement function;

wherein the memory also stores a software program which is executable to generate configuration information based on the block diagram, wherein the configuration information describes a hardware implementation of the block diagram; and

a device coupled to the computer system, wherein the device includes;

an input for acquiring a signal from an external source;

a programmable hardware element, wherein the programmable hardware element in the device is configurable utilizing the configuration information; and

programmable switching circuitry coupled to the programmable hardware element, wherein the programmable switching circuitry in the device is configurable utilizing the configuration information;

wherein after being configured the programmable hardware element and the programmable switching circuitry implement a hardware implementation of the block diagram;

wherein the programmable hardware element and the programmable switching circuitry are operable to perform the measurement function on an acquired signal.

55. The reconfigurable measurement system of claim 54,

wherein the configuration information includes a hardware architecture file;

wherein the programmable hardware element is operable to be configured using the hardware architecture file.

56. The reconfigurable measurement system of claim 54,

wherein the configuration information includes a programmable switching circuitry configuration file;

wherein the programmable switching circuitry is operable to be configured using the programmable switching circuitry configuration file.

57. The reconfigurable measurement system of claim 54,

wherein the block diagram includes a first portion that specifies a configuration for the programmable hardware element, and wherein the block diagram includes a second portion that specifies a configuration for the programmable switching circuitry;

wherein the configuration information includes a hardware architecture file and a programmable switching circuitry configuration file;

wherein the software program is executable to generate the hardware architecture file based on the first portion of the block diagram; and

wherein the software program is executable to generate the programmable switching circuitry configuration file based on the second portion of the block diagram.

58. The reconfigurable measurement system of claim 54, wherein the block diagram comprises a graphical program.

59. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, wherein the device also includes one or more programmable analog/digital (A/D) and/or digital/analog (D/A) converters coupled to the programmable hardware element, the method comprising:

creating a block diagram in response to user input, wherein the block diagram specifies at least a portion of the measurement function;

generating a hardware architecture file based on at least a portion of the block diagram, wherein the hardware architecture file describes a hardware implementation of the at least a portion of the block diagram;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the one or more programmable A/D and/or D/A converters in the device;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element and the one or more programmable A/D and/or D/A converters in the device executing to perform the measurement function on the signal.

60. The method of claim 59,

wherein said configuring the one or more programmable A/D and/or D/A converters comprises configuring the one or more programmable A/D and/or D/A converters utilizing the hardware architecture file.

61. The method of claim 59, further comprising:

creating a programmable A/D and/or D/A converter configuration file which describes a configuration for the one or more programmable A/D and/or D/A converters;

wherein said configuring the one or more programmable A/D and/or D/A converters comprises configuring the one or more programmable A/D and/or D/A converters utilizing the programmable A/D and/or D/A converter configuration file.

62. The method of claim 59,

wherein the block diagram includes a first portion that specifies a configuration for the programmable hardware element, and wherein the block diagram includes a second portion that specifies a configuration for the one or more programmable A/D and/or D/A converters;

wherein said generating comprises generating the hardware architecture file based on the first portion of the block diagram; and

wherein said configuring the one or more programmable A/D and/or D/A converters comprises configuring the one or more programmable A/D and/or D/A converters based on the second portion of the block diagram.

63. The method of claim 59, wherein the device also includes a processor and memory coupled to the programmable hardware element;

the method further comprising;

storing an executable program in the memory of the device for execution by the processor on the device, wherein the executable program operates with the programmable hardware element and one or more programmable A/D and/or D/A converters to perform the measurement function.

64. The method of claim 59, wherein the block diagram comprises a graphical program.

65. A reconfigurable measurement system, comprising:

a computer system comprising a processor, memory and a display;

wherein the memory stores a block diagram, wherein the block diagram implements a measurement function;

wherein the memory also stores a software program which is executable to generate configuration information based on the block diagram, wherein the configuration information describes a hardware implementation of the block diagram; and

a device coupled to the computer system, wherein the device includes;

an input for acquiring a signal from an external source;

a programmable hardware element, wherein the programmable hardware element in the device is configurable utilizing the configuration information; and

one or more programmable A/D and/or D/A converters coupled to the programmable hardware element, wherein the one or more programmable A/D and/or D/A converters in the device are configurable utilizing the configuration information;

wherein after being configured the programmable hardware element and the one or more programmable A/D and/or D/A converters implement a hardware implementation of the block diagram;

wherein the programmable hardware element and the one or more programmable A/D and/or D/A converters are operable to perform the measurement function on an acquired signal.

66. The reconfigurable measurement system of claim 65,

wherein the configuration information includes a hardware architecture file;

wherein the programmable hardware element is operable to be configured using the hardware architecture file.

67. The reconfigurable measurement system of claim 65,

wherein the configuration information includes a programmable A/D and/or D/A converters configuration file;

wherein the one or more programmable A/D and/or D/A converters are operable to be configured using the programmable A/D and/or D/A converter configuration file.

68. The reconfigurable measurement system of claim 65,

wherein the block diagram includes a first portion that specifies a configuration for the programmable hardware element, and wherein the block diagram includes a second portion that specifies a configuration for the one or more programmable A/D and/or D/A converters;

wherein the configuration information includes a hardware architecture file and a programmable A/D and/or D/A converter configuration file;

wherein the software program is executable to generate the hardware architecture file based on the first portion of the block diagram; and

wherein the software program is executable to generate the programmable A/D and/or D/A converter configuration file based on the second portion of the block diagram.

69. The reconfigurable measurement system of claim 65, wherein the block diagram comprises a graphical program.

70. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, wherein the device also includes one or more field programmable analog arrays (FPAAs) coupled to the programmable hardware element, the method comprising:

creating a block diagram in response to user input, wherein the block diagram specifies at least a portion of the measurement function;

generating a hardware architecture file based on at least a portion of the block diagram, wherein the hardware architecture file describes a hardware implementation of the at least a portion of the block diagram;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the one or more FPAAs in the device;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element and the one or more FPAAs in the device executing to perform the measurement function on the signal.

71. The method of claim 70,

wherein said configuring the one or more FPAAs comprises configuring the one or more FPAAs utilizing the hardware architecture file.

72. The method of claim 70, further comprising:

creating a FPAA configuration file which describes a configuration for the one or more FPAAs;

wherein said configuring the one or more FPAAs comprises configuring the one or more FPAAs utilizing the FPAA configuration file.

73. The method of claim 70,

wherein the block diagram includes a first portion that specifies a configuration for the programmable hardware element, and wherein the block diagram includes a second portion that specifies a configuration for the one or more FPAAs;

wherein said generating comprises generating the hardware architecture file based on the first portion of the block diagram; and

wherein said configuring the one or more FPAAs comprises configuring the one or more FPAAs based on the second portion of the block diagram.

74. The method of claim 70, wherein the device also includes a processor and memory coupled to the programmable hardware element;

the method further comprising;

storing an executable program in the memory of the device for execution by the processor on the device, wherein the executable program operates with the programmable hardware element and the one or more FPAAs to perform the measurement function.

75. The method of claim 70, wherein the block diagram comprises a graphical program.

76. A reconfigurable measurement system, comprising:

a computer system comprising a processor, memory and a display;

wherein the memory stores a block diagram, wherein the block diagram implements a measurement function;

wherein the memory also stores a software program which is executable to generate configuration information based on the block diagram, wherein the configuration information describes a hardware implementation of the block diagram; and

a device coupled to the computer system, wherein the device includes;

an input for acquiring a signal from an external source;

a programmable hardware element, wherein the programmable hardware element in the device is configurable utilizing the configuration information; and

one or more FPAAs coupled to the programmable hardware element, wherein the one or more FPAAs in the device is configurable utilizing the configuration information;

wherein after being configured the programmable hardware element and the one or more FPAAs implement a hardware implementation of the block diagram;

wherein the programmable hardware element and the one or more FPAAs are operable to perform the measurement function on an acquired signal.

77. The reconfigurable measurement system of claim 76,

wherein the configuration information includes a hardware architecture file;

wherein the programmable hardware element is operable to be configured using the hardware architecture file.

78. The reconfigurable measurement system of claim 76,

wherein the configuration information includes a FPAA configuration file;

wherein the one or more FPAAs is operable to be configured using the FPAA configuration file.

79. The reconfigurable measurement system of claim 76,

wherein the block diagram includes a first portion that specifies a configuration for the programmable hardware element, and wherein the block diagram includes a second portion that specifies a configuration for the one or more FPAAs;

wherein the configuration information includes a hardware architecture file and more FPAA configuration file;

wherein the software program is executable to generate the hardware architecture file based on the first portion of the block diagram; and

wherein the software program is executable to generate the FPAA configuration file based on the second portion of the block diagram.

80. The reconfigurable measurement system of claim 76, wherein the block diagram comprises a graphical program.

81. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, one or more programmable transceivers, and a processor and memory, the method comprising:

creating a block diagram in response to user input, wherein the block diagram specifies at least a portion of the measurement function;

receiving user input specifying a first portion of the block diagram to be implemented in the programmable hardware element, a second portion of the block diagram to be implemented by the one or more programmable transceivers, and a third portion of the block diagram to be implemented by the processor;

generating a hardware architecture file based on the first portion of the block diagram, wherein the hardware architecture file describes a hardware implementation of the first portion of the block diagram;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the one or more programmable transceivers in the device based on the second portion of the block diagram;

storing a software program based on the third portion of the block diagram in the memory for execution by the processor;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element, the one or more programmable transceivers, and the processor in the device executing to perform the measurement function on the signal.

82. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, one or more programmable transceivers, and a processor and memory, the method comprising:

creating a first block diagram in response to user input, wherein the first block diagram specifies a first portion of the measurement function;

creating a second block diagram in response to user input, wherein the second block diagram specifies a second portion of the measurement function;

creating a third block diagram in response to user input, wherein the third block diagram specifies a third portion of the measurement function;

receiving user input specifying the first block diagram to be implemented in the programmable hardware element, the second block diagram to be implemented by the one or more programmable transceivers, and the third block diagram to be implemented by the processor and memory;

generating a hardware architecture file based on the first block diagram, wherein the hardware architecture file describes a hardware implementation of the first block diagram;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the one or more programmable transceivers in the device based on the second block diagram;

storing a software program based on the third block diagram in the memory for execution by the processor;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element, the one or more programmable transceivers, and the processor and memory in the device executing to perform the measurement function on the signal.

83. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, one or more programmable transceivers, and a device processor and device memory, wherein the device is coupled to a computer system which includes a host processor and a host memory, the method comprising:

creating a block diagram in response to user input, wherein the block diagram specifies the measurement function;

receiving user input specifying a first portion of the block diagram to be implemented in the programmable hardware element, a second portion of the block diagram to be implemented by the one or more programmable transceivers, a third portion of the block diagram to be implemented by the device processor, and a fourth portion to be implemented by the host processor;

generating a hardware architecture file based on the first portion of the block diagram, wherein the hardware architecture file describes a hardware implementation of the first portion of the block diagram;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the one or more programmable transceivers in the device based on the second portion of the block diagram;

storing a device software program based on the third portion of the block diagram in the device memory for execution by the device processor;

storing a host software program based on the fourth portion of the block diagram in the host memory for execution by the host processor;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element, the one or more programmable transceivers, the device processor, and the host processor executing to perform the measurement function on the signal.

84. A computer-implemented method for configuring a device to perform a measurement function, wherein the device includes a programmable hardware element, wherein the device also includes one or more programmable transceivers coupled to the programmable hardware element, the method comprising:

creating a block diagram in response to user input, wherein the block diagram specifies at least a portion of the measurement function;

executing a utility to automatically specify a first portion of the block diagram to be implemented in the programmable hardware element and a second portion of the block diagram to be implemented by the one or more programmable transceivers;

generating a hardware architecture file based on the first portion of the block diagram, wherein the hardware architecture file describes a hardware implementation of the first portion of the block diagram;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the one or more programmable transceivers in the device based on the second portion of the block diagram;

the device acquiring a signal from an external source after said configuring; and

the programmable hardware element and the one or more programmable transceivers in the device executing to perform the measurement function on the signal.

85. A computer-implemented method for configuring a device to perform an automation function, wherein the device includes a programmable hardware element, wherein the device also includes one or more programmable transceivers coupled to the programmable hardware element, the method comprising:

creating a block diagram in response to user input, wherein the block diagram specifies at least a portion of the automation function;

generating a hardware architecture file based on at least a portion of the block diagram, wherein the hardware architecture file describes a hardware implementation of the at least a portion of the block diagram;

configuring the programmable hardware element in the device utilizing the hardware architecture file, wherein after said configuring the programmable hardware element implement a hardware implementation of the at least a portion of the block diagram;

configuring the one or more programmable transceivers in the device;

the device acquiring a signal from an external source after said configuring;

the programmable hardware element and the one or more programmable transceivers in the device executing to perform the automation function on the signal; and

the device generating a control signal in response to said executing.

86. The method of claim 85,

wherein said configuring the one or more programmable transceivers comprises configuring the one or more programmable transceivers utilizing the hardware architecture file.

87. The method of claim 85, further comprising:

creating a programmable transceiver configuration file which describes a configuration for the one or more programmable transceivers;

wherein said configuring the one or more programmable transceivers comprises configuring the one or more programmable transceivers utilizing the programmable transceiver configuration file.

88. The method of claim 85,

wherein the block diagram includes a first portion that specifies a configuration for the programmable hardware element, and wherein the block diagram includes a second portion that specifies a configuration for the one or more programmable transceivers;

wherein said generating comprises generating the hardware architecture file based on the first portion of the block diagram; and

wherein said configuring the one or more programmable transceivers comprises configuring the one or more programmable transceivers based on the second portion of the block diagram.

89. The method of claim 85, wherein the device also includes a processor and memory coupled to the programmable hardware element;

the method further comprising;

storing an executable program in the memory of the device for execution by the processor on the device, wherein the executable program operates with the programmable hardware element and the one or more programmable transceivers to perform the automation function.

90. The method of claim 85, wherein the block diagram comprises a graphical program.

91. The method of claim 85,

wherein the device operates as a controller;

and

wherein the external source is a unit under test.

92. A reconfigurable automation system, comprising:

a computer system comprising a processor, memory and a display;

wherein the memory stores a block diagram, wherein the block diagram implements a automation function;

wherein the memory also stores a software program which is executable to generate configuration information based on the block diagram, wherein the configuration information describes a hardware implementation of the block diagram; and

a device coupled to the computer system, wherein the device includes;

an input for acquiring a signal from an external source;

an output for generating a control signal;

a programmable hardware element, wherein the programmable hardware element in the device is configurable utilizing the configuration information; and

one or more programmable transceivers coupled to the programmable hardware element, wherein the one or more programmable transceivers in the device are configurable utilizing the configuration information;

wherein after being configured the programmable hardware element and the one or more programmable transceivers implement a hardware implementation of the block diagram;

wherein the programmable hardware element and the one or more programmable transceivers are operable to perform the automation function on an acquired signal and generate a control signal in response thereto.

93. The reconfigurable automation system of claim 92,

wherein the configuration information includes a hardware architecture file;

wherein the programmable hardware element is operable to be configured using the hardware architecture file.

94. The reconfigurable automation system of claim 92,

wherein the configuration information includes a programmable transceiver configuration file;

wherein the one or more programmable transceivers are operable to be configured using the programmable transceiver configuration file.

95. The reconfigurable automation system of claim 92,

wherein the block diagram includes a first portion that specifies a configuration for the programmable hardware element, and wherein the block diagram includes a second portion that specifies a configuration for the one or more programmable transceivers;

wherein the configuration information includes a hardware architecture file and a programmable transceiver configuration file;

wherein the software program is executable to generate the hardware architecture file based on the first portion of the block diagram; and

wherein the software program is executable to generate the programmable transceiver configuration file based on the second portion of the block diagram.

96. The reconfigurable automation system of claim 92,

wherein the device also includes a processor and memory coupled to the programmable hardware element;

wherein the memory of the devices stores an executable program for execution by the processor on the device, wherein the executable program operates with the programmable hardware element and the one or more programmable transceivers to perform the automation function.

97. The reconfigurable automation system of claim 92,

wherein the software program is executable to generate the executable program based on the block diagram.

98. The reconfigurable automation system of claim 92, wherein the block diagram comprises a graphical program.

99. The reconfigurable automation system of claim 92,

wherein the memory of the computer system stores a graphical design environment for creating the block diagram.

100. The reconfigurable automation system of claim 92,

wherein the block diagram comprises a data flow block diagram;

wherein the memory of the computer system stores a graphical data flow programming development environment for creating the data flow block diagram.