Dummy fill for integrated circuits
DCFirst Claim
1. A method comprisingenabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps,the generation of a strategy or the placing of dummy fill features being based on(a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design,(b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit and(c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design,the use of the model and dimensional characteristics, and the simulation or analysis of the electrical impact analysis being embedded as part of the generation of the strategy for placing dummy fill features.
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Abstract
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
355 Citations
79 Claims
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1. A method comprising
enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the use of the model and dimensional characteristics, and the simulation or analysis of the electrical impact analysis being embedded as part of the generation of the strategy for placing dummy fill features.
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2. A method comprising
enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit, and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the fabrication process floe for which the strategy is being generated comprising other than an oxide chemical mechanical polishing process.
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3. A method comprising
enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit, and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the fabrication process flow for which the strategy is being generated comprising two or more stages of fabrication.
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4. A method comprising
enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit, and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the fabrication process flow for which the strategy is being generated comprising a polishing or planarization process in which more than one material is removed.
Specification