MOS electronic article surveillance, RF and/or RF identification tag/device, and methods for making and using the same

• US 7,152,804 B1
• Filed: 07/06/2004
• Issued: 12/26/2006
• Est. Priority Date: 03/15/2004
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovlo Incorporated
• Inventors: Rockenberger, Joerg, Cleeves, James Montague, MacKenzie, J. Devin, Pavate, Vik, Davis, Max, Gudeman, Christopher, Good, Dan, Zurcher, Fabio
• Primary Examiner(s): Lee, Michael G.
• Assistant Examiner(s): TRAIL, ALLYSON NEEL
• Application Number:
  US10/885,283
• Time in Patent Office: 903 Days
• Field of Search: 235/492, 340/572.3, 340/572.5, 438/68, 438/398, 257/410
• US Class Current: 235/492
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/07752 using an interposer
• CPC Class Codes: G08B 13/2417 having a radio frequency identification chip
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/82047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A RF MOS- or nonlinear device-based surveillance and/or identification tag, and methods for its manufacture and use. The tag generally includes (a) an inductor, (b) a first capacitor plate coupled to the inductor, (c) a dielectric film on the first capacitor plate, (d) a semiconductor component on the dielectric film, and (e) a conductor that provides electrical communication between the semiconductor component and the inductor. The method of manufacture generally includes (1) depositing a semiconductor material (or precursor) on a dielectric film; (2) forming a semiconductor component from the semiconductor material/precursor; (3) forming a conductive structure at least partly on the semiconductor component; and (4) etching the electrically functional substrate to form (i) an inductor and/or (ii) a second capacitor plate. The method of use generally includes (i) causing/inducing a current in the present tag sufficient for it to generate detectable electromagnetic radiation; (ii) detecting the radiation; and optionally, (iii) selectively deactivating the tag. The present invention advantageously provides a low cost EAS/RFID tag capable of operating at MHz frequencies and in frequency division and/or frequency multiplication modes.

Claims

1. A surveillance and/or identification device, comprising:

a) a first capacitor plate;

b) an inductor electrically connected to said first capacitor plate;

c) a dielectric film on said first capacitor plate;

d) a semiconductor component on said dielectric film, said semiconductor component being capacitively coupled to said first capacitor plate;

e) a conductor electrically connected to said semiconductor component, providing electrical communication between said semiconductor component and said inductor; and

f) a second capacitor plate complementary to said first capacitor plate, wherein said device includes a non-linear capacitor comprising said second capacitor plate, said semiconductor component, said first capacitor plate, and a portion of dielectric film between said semiconductor component and said first capacitor plate.

2. The device of claim 1, wherein said semiconductor component comprises a first Group IVA element.

3. The device of claim 2, wherein said first Group IVA element comprises silicon.

4. The device of claim 2, wherein said first Group IVA element consists essentially of silicon.

5. The device of claim 4, wherein said semiconductor component comprises a first layer consisting essentially of silicon.

6. The device of claim 2, wherein said first Group IVA element consists essentially of silicon and/or germanium.

7. The device of claim 1, wherein said second capacitor plate has a thickness of from 30 nm to 5000 nm.

8. The device of claim 7, wherein said second capacitor plate thickness is from 50 nm to 2000 nm.

9. The device of claim 1, wherein said inductor comprises a first metal.

10. The device of claim 9, wherein said first metal comprises aluminum.

11. The device of claim 10, wherein said first metal consists essentially of aluminum.

12. The device of claim 9, wherein said dielectric film comprises a corresponding oxide of said metal.

13. The device of claim 12, wherein said dielectric film consists essentially of said corresponding metal oxide.

14. The device of claim 1, wherein said inductor has a nominal thickness of from 20 to 100 μ

m.

15. The device of claim 1, wherein said inductor has a resistivity of 0.1–

10 μ

ohm-cm.

16. The device of claim 1, wherein said dielectric film has a thickness of from 50 to 400 Å

.

17. The device of claim 1, wherein said dielectric film has a breakdown voltage of from about 5 V to less than 30 V.

18. The device of claim 17, wherein said dielectric film has a breakdown voltage of from 10 V to 20 V.

19. The device of claim 1, wherein said conductor comprises a second metal.

20. The device of claim 19, wherein said second metal comprises aluminum, silver, gold, or nickel.

21. The device of claim 20, wherein said second metal consists essentially of aluminum, silver, gold, or nickel.

22. The device of claim 1, further comprising an interlayer dielectric between said dielectric film and at least part of said conductor.

23. The device of claim 22, wherein said semiconductor element has a periphery, and said interlayer dielectric is also between said periphery and said conductor.

24. The device of claim 22, wherein said interlayer dielectric comprises a via over at least part of said semiconductor element.

25. The device of claim 24, wherein said semiconductor element is entirely within said via.

26. The device of claim 22, wherein said interlayer dielectric comprises an oxide and/or nitride of a second Group IVA element.

27. The device of claim 26, wherein said second Group IVA element consists essentially of silicon.

28. The device of claim 26, wherein said interlayer dielectric consists essentially of silicon dioxide.

29. The device of claim 1, further comprising a passivation layer over said conductor.

30. The device of claim 22, further comprising a passivation layer over said conductor and said interlayer dielectric.

31. The device of claim 1, further comprising a support and/or backing layer on a surface of said inductor opposite said dielectric film.

32. A method of detecting items, comprising the steps of:

a) causing or inducing a current in the device of claim 1 sufficient for the device to radiate detectable electromagnetic radiation;

b) detecting said detectable electromagnetic radiation; and

c) optionally, selectively deactivating said device.

33. The method of claim 32, wherein said detectable electromagnetic radiation has a frequency that is an integer multiple or an integer divisor of a fundamental frequency of an oscillating electromagnetic field or wave applied to said device.

34. The method of claim 32, wherein inducing or causing said current comprises generating an oscillating electromagnetic field or wave in a detection zone, said oscillating electromagnetic field or wave having a fundamental frequency, and allowing said device to be brought into said detection zone.

35. The method of claim 32, further comprising attaching, affixing or including the device on or in said item.

36. The method of claim 32, wherein said device is nonlinearly polarized in response to an applied electromagnetic field having sufficient strength and an effective oscillating frequency to induce said current in the device.

37. A surveillance and/or identification device comprising:

a) a first capacitor plate;

b) an inductor electrically connected to said first capacitor plate;

c) a dielectric film on said first capacitor plate;

d) a semiconductor component on said dielectric film, said semiconductor component being capacitively coupled to said first capacitor plate, wherein said semiconductor component comprises a first layer consisting essentially of silicon and a second layer of metal silicide or doped silicon on said first layer;

e) a conductor electrically connected to said semiconductor component, providing electrical communication between said semiconductor component and said inductor.

38. The device of claim 37, further comprising a second capacitor plate complementary to said first capacitor plate.

39. The device of claim 38, wherein said second capacitor plate is in electrical communication with said conductor.

40. The device of claim 39, wherein said second capacitor plate has a major surface in contact with said semiconductor component.

41. The device of claim 38, including a non-linear capacitor comprising said second capacitor plate, said semiconductor component, said first capacitor plate, and a portion of dielectric film between said semiconductor component and said first capacitor plate.

42. A method for making a surveillance and/or identification device, comprising the steps of:

a) depositing a liquid-phase Group IVA element precursor ink on a dielectric film, said dielectric film being on an electrically functional substrate;

b) forming a semiconductor component from said liquid-phase Group IVA element precursor ink;

c) forming a conductive structure at least partly on said semiconductor component, configured to provide electrical communication between said semiconductor component and said electrically functional substrate; and

d) etching said electrically functional substrate to form an inductor and/or a second capacitor plate capacitively coupled to said semiconductor component under one or more predetermined conditions.

43. The method of claim 42, wherein said depositing step comprises printing said liquid-phase Group IVA element precursor ink on said dielectric film.

44. The method of claim 43, wherein printing comprises inkjet printing, microspotting, stenciling, stamping, syringe dispensing, pump dispensing, screen printing, gravure printing, offset printing, flexography, laser forward transfer, or local laser CVD.

45. The method of claim 42, wherein said step of forming said semiconductor component comprises curing said Group IVA element precursor.

46. The method of claim 45, wherein said step of forming said semiconductor component further comprises drying said liquid-phase Group IVA element precursor ink before said curing.

47. The method of claim 45, wherein said Group IVA element precursor comprises a compound of the formula A_nH_n+y, where n is from 3 to 12, each A is independently Si or Ge, and y is an even integer of from n to 2n+2.

48. The method of claim 47, wherein said Group IVA element precursor comprises a compound of the formula (AH_z)_n, where n is from 5 to 10, each A is independently Si or Ge, and each of the n instances of z is independently 1 or 2.

49. The method of claim 42, wherein said liquid-phase Group IVA element precursor ink further comprises a solvent.

50. The method of claim 49, wherein said solvent comprises a cycloalkane.

51. The method of claim 42, further comprising recrystallizing to improve the mobility of the semiconductor.

52. The method of claim 42, further comprising the step of forming a second capacitor plate on said semiconductor element, such that said second capacitor plate is (i) in electrical communication with said conductive structure and (ii) complementary to said first capacitor plate.

53. The method of claim 42, wherein said electrically functional substrate comprises a metal sheet or metal foil.

54. The method of claim 53, wherein said metal sheet or metal foil has a nominal thickness of 20–

100 μ

m and a resistivity of 0.1–

10 μ

ohm-cm.

55. The method of claim 53, wherein said metal sheet or metal foil comprises aluminum.

56. The method of claim 53, further comprising the step of forming said dielectric film on said metal sheet or metal foil.

57. The method of claim 56, wherein said step of forming said dielectric film comprises anodizing said metal sheet or metal foil.

58. The method of claim 42, wherein said dielectric film has a thickness of from 50 to 400 Å

and a breakdown voltage of from 10 to 20 V.

59. The method of claim 42, wherein said etching forms said inductor.

60. The method of claim 59, wherein said etching further forms said second capacitor plate.

61. The method of claim 60, wherein said one or more predetermined conditions comprises a predetermined threshold voltage.

62. The method of claim 42, further comprising the step of adding a support or backing to said etched electrically functional substrate.

63. The method of claim 42, wherein said step of forming said conductor comprises depositing said conductor onto at least part of said electrically functional substrate and said semiconductor component, and etching said conductor.

64. The method of claim 42, further comprising the step of depositing an interlayer dielectric on said dielectric film.

65. The method of claim 64, wherein said step of depositing said interlayer dielectric is performed after said step of forming said semiconductor component, and said interlayer dielectric is also deposited on at least part of said semiconductor component.

66. The method of claim 64, further comprising the step of forming a via in said interlayer dielectric sufficient to expose at least part of said semiconductor component.

67. The method of claim 64, wherein said step of depositing said interlayer dielectric is performed before said step of forming said semiconductor component.

68. The method of claim 64, wherein said step of depositing said interlayer dielectric comprises the steps of (i) depositing a liquid-phase interlayer dielectric precursor ink on said dielectric film, and (ii) drying and/or curing said interlayer dielectric precursor to form said interlayer dielectric.

69. The method of claim 68, wherein said liquid-phase interlayer dielectric precursor ink is deposited on said dielectric film by printing said liquid-phase interlayer dielectric precursor ink such that an opening is formed into which said semiconductor component or semiconductor component precursor is deposited.

70. The method of claim 68, wherein said liquid-phase interlayer dielectric precursor ink comprises a compound of the formula A_nH_y, where n is from 3 to 12, each A is independently Si or Ge, and y is an even integer of from n to 2n+2.

71. The method of claim 68, comprising curing said interlayer dielectric precursor in an oxidizing atmosphere to form said interlayer dielectric.

72. The method of claim 64, wherein said interlayer dielectric has a thickness of at least one micron.

73. The method of claim 64, further comprising the step of forming a passivation layer over said interlayer dielectric and said conductive structure.

74. A method of for making a surveillance and/or identification device, comprising the steps of:

a) depositing a semiconductor material or semiconductor material precursor on a dielectric film, said dielectric film being on an electrically functional substrate;

b) forming a semiconductor component from said semiconductor material or semiconductor material precursor;

c) recrystallizing said semiconductor component sufficiently to improve its carrier mobility;

d) forming a conductive structure at least partly on said semiconductor component, configured to provide electrical communication between said semiconductor component and said electrically functional substrate; and

e) etching said electrically functional substrate to form an inductor and/or a second capacitor plate capacitively coupled to said semiconductor component under one or more predetermined conditions.

75. The method of claim 74, wherein said semiconductor material or semiconductor material precursor comprises a Group IVA element.

76. The method of claim 75, wherein said depositing step comprises depositing a liquid-phase Group IVA element precursor ink on said dielectric film.

77. The method of claim 74, further comprising doping said semiconductor component at least near an interface between the semiconductor component and the conductive structure, to an extent sufficient to reduce a resistance and/or potential barrier in said device.

78. A method of for making a surveillance and/or identification device, comprising the steps of:

a) depositing a semiconductor material or semiconductor material precursor on a dielectric film, said dielectric film being on an electrically functional substrate;

b) forming a semiconductor component from said semiconductor material or semiconductor material precursor;

c) forming a conductor at least partly on said semiconductor component by printing a conductor ink onto said dielectric film and said semiconductor component, said conductor configured to provide electrical communication between said semiconductor component and said electrically functional substrate; and

d) etching said electrically functional substrate to form an inductor and/or a second capacitor plate capacitively coupled to said semiconductor component under one or more predetermined conditions.

79. The method of claim 78, wherein said step of forming said conductor further comprises the step of curing said conductor ink.