Semiconductor device and method for fabricating the same

• US 7,153,715 B2
• Filed: 02/10/2005
• Issued: 12/26/2006
• Est. Priority Date: 11/13/2001
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ueda, Tetsuzo
• Primary Examiner(s): LEE, HSIEN MING
• Application Number:
  US11/053,874
• Publication Number:
  US 20050199901A1
• Time in Patent Office: 684 Days
• Field of Search: 438/458, 438/46, 438/47, 438/93, 257/14, 257/110, 257/22
• US Class Current: 438/46
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: C30B 25/183 being provided with a buffer layer, e.g. a lattice matching layer
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02472 Oxides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01S 2301/173 The laser chip comprising special buffer layers, e.g. dislocation prevention or reduction
• CPC Class Codes: H01S 5/0202 Cleaving
• CPC Class Codes: H01S 5/0213 Sapphire, quartz or diamond based substrates
• CPC Class Codes: H01S 5/0215 Bonding to the substrate
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/0218 Substrates comprising semiconducting materials from different groups of the periodic system than the active layer
• CPC Class Codes: H01S 5/320225 polar orientation
• CPC Class Codes: H01S 5/34333 : with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

A spacer layer is formed on a single-crystal substrate and an epitaxially grown layer composed of a group III-V compound semiconductor layer containing a nitride or the like is further formed on the spacer layer. The epitaxially grown layer is adhered to a recipient substrate. The back surface of the single-crystal substrate is irradiated with a light beam such as a laser beam or a bright line spectrum from a mercury vapor lamp such that the epitaxially grown layer and the single-crystal substrate are separated from each other. Since the forbidden band of the spacer layer is smaller than that of the single-crystal substrate, it is possible to separate the thin semiconductor layer from the substrate by decomposing or fusing the spacer layer, while suppressing the occurrence of a crystal defect or a crack in the epitaxially grown layer.

Claims

1. A method for fabricating a semiconductor device having a semiconductor layer formed by epitaxial growth from a single-crystal substrate, the method comprising the steps of:

(a) forming a spacer layer having an optical band gap smaller than an optical band gap of a lowermost portion of the semiconductor layer such that an upper surface of the single-crystal substrate is covered with the spacer layer;

(b) forming the semiconductor layer on the spacer layer; and

(c) irradiating the spacer layer with a light beam having an energy smaller than an optical band gap of the single-crystal substrate and larger than the optical band gap of the spacer layer through a back surface of the single-crystal substrate to separate the semiconductor layer from the single-crystal substrate,

wherein the step (a) includes a sub-step of forming a InGaN layer as the spacer layer, and

the step (b) includes a sub-step of composing the lowermost portion of the semiconductor layer of an Al_yGa<sub>1−

y</sub>N layer (0<

y≦

1) and a sub-step of adjusting a thickness of the semiconductor layer to a range not less than 0.5 μ

m and less than 4 μ

m.