CMOS image sensor

• US 7,153,720 B2
• Filed: 06/01/2005
• Issued: 12/26/2006
• Est. Priority Date: 12/09/2002
• Status: Active Grant

• Current Assignee: Quantum Semiconductor LLC
• Original Assignee: Quantum Semiconductor LLC
• Inventors: Augusto, Carlos J. R. P.
• Primary Examiner(s): Malsawma, Lex H.
• Application Number:
  US11/142,783
• Publication Number:
  US 20050233493A1
• Time in Patent Office: 573 Days
• Field of Search: 438/69, 438/75
• US Class Current: 438/69
• CPC Class Codes: G02B 1/005 made of photonic crystals or photonic band gap materials photonic band-gap structures or photonic lattices in integrated optics G02B6/1225; photonic band-gap structures or photonic lattices in optical fibres G02B6/02295
• CPC Class Codes: G02B 5/008 Surface plasmon devices diffractive gratings with a pitch less than or comparable to the wavelength G02B5/1809; surface plasmons in integrated optics G02B6/1226; optical analysis of materials by means of surface plasmons G01N21/553
• CPC Class Codes: G02B 5/201 in the form of arrays
• CPC Class Codes: G02B 5/208 for use with infrared or ultraviolet radiation, e.g. for separating visible light from infrared and/or ultraviolet radiation
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/02165 using interference filters, e.g. multilayer dielectric filters interference filters G02B5/28
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type

Abstract

Light sensing devices are monolithically integrates with CMOS devices on Thin-Film Silicon-On-insulator (TF-SOI) or Thin-Film Germanium-On-Insulator (TF-GeOI) substrates. Photo-diode active layers are epitaxially grown on the front-side of the substrate and after full processing of the front-side of the substrate, the substrate material is removed under the buried insulator (buried oxide). Monolithically integrated structures are then fabricated on the back of the buried oxide. The back-side is then bonded to a new substrate that is transparent to the wavelengths of interest. For example, quartz, sapphire, glass, or plastic, are suitable for the visible range. Back-side illumination of the sensor matrix is thereby allowed, with light traveling through the structures fabricated on the back of the substrate, opposite to the side on which CMOS is made.

Claims

1. A method of constructing process architecture to fabricate back-side illuminated image sensor matrices, the process architecture comprising fully-depleted CMOS devices, and photo-diodes incorporating epitaxially grown regions, the method comprising:

(a) selecting a Thin-Film Silicon-On-Insulator (TF-SOI) or Thin-Film Germanium-On-Insulator (TF-GeOI or TF-GOI) substrate, comprising a top thin semiconductor film, a buried insulator comprising a back surface that faces a bottom thick semiconductor substrate;

(b) fabricating the fully-depleted CMOS devices and circuitry incorporating the fully-depleted CMOS devices on the top thin semiconductor film;

(c) Epitaxially growing photo-diode active layers on the top thin semiconductor film;

(d) fabricating dense metal interconnects over each of the image sensor matrices, including over the photo-diode regions, on a top of the thin semiconductor film;

(e) removing the bottom thick semiconductor substrate, after full processing of a front-side of the top thin semiconductor film;

(f) fabricating monolithically integrated structures on the back surface of the buried insulator, aligned to the dense metal interconnects made on the top thin semiconductor film;

(g) bonding to a new mechanical substrate that is transparent to wavelengths of interest, of the back surface of the buried insulator after fabricating the monolithically integrated structures; and

(h) dicing and packaging each of the fully-depleted CMOS devices, or wafer-level packaging followed by separation of individual CMOS image sensor matrix chips.

2. The method of claim 1, additionally comprising embedding, with the monolithically integrated structures fabricated on the back surface of the buried insulator, at least one conventional color filter between the buried insulator and the transparent new mechanical substrate.

3. The method of claim 1, including making in-pixel homojunction or heterojunction epitaxial capacitors directly on the epitaxially grown photo-diode active layers.

4. The method of claim 1, including making in-pixel MOS capacitors directly on the epitaxially grown photo-diode active layers.

5. The method of claim 1, including making in-pixel MIM capacitors over an area of a pixel, during the fabrication of dense metal interconnects.

6. The method of claim 1, wherein the monolithically integrated structures are monolithically integrated Surface Plasmon Polariton (SPP) “

Light Funnel”

structures.

7. The method of claim 6, wherein the Surface Plasmon Polariton (SPP) “

Light Funnel”

structures are arranged into 1D or 2D arrays, on the back surface of the buried insulator, the method comprising;

forming a thin-film on the back surface of the buried insulator, of a first insulating material that is transparent to the wavelengths of interest, as a barrier to protect said buried insulator from possible physio-chemical damage during subsequent processing;

forming a thin-film of a second insulating material, having a low index of refraction for the wavelengths of interest;

forming holes across the entire thickness of the second insulating material film;

filling the holes with the first insulating material;

forming a thin-film of a third insulating material, having a high index of refraction for the wavelengths of interest, thereby filling the holes and forming a T-shaped cross-section;

positioning a bottom of the holes filled with the third insulating material as closely as possible to the absorption region of a photo-sensor, leading to selecting reduced thickness values for the buried insulator of a TF-SOI wafer and for the first insulating material barrier film;

forming a thin-film of conducting material over the film of the second insulating material;

patterning the thin film of the conducting material over the third insulating material into an array of isolated pixels of regular shapes that may be replicated to completely fill a surface, and positioning the array of isolated pixels at an image plane of a lens;

covering an exposed surface of the isolated pixels with predetermined insulator materials having predetermined dielectric constants to tune a wavelength of operation;

exciting resonant surface plasmon polaritons by electromagnetic radiation impinging on a top surface of the isolated pixels; and

propagating an excitation to the bottom of the holes, where the electromagnetic radiation is coupled to, and absorbed by, a photo-sensor.

8. The method of claim 7, wherein a diameter of the holes where light is leaked out to the photo-sensors, is much smaller than the wavelength of light, without an occurrence of diffraction, and a diameter of the photo-sensors, fabricated on the top semiconductor film, is identical to a diameter of said holes plus an additional margin to accommodate a possible misalignment between said holes and said photo-sensors, resulting from separate patterning steps for respective fabrication.

9. The method of claim 8, additionally comprising perforating the thin-film of conducting material with slits and holes of desirable shapes, size and pitch in order to enhance wavelength selectivity and polarization selectivity.

10. The method of claim 7, additionally comprising perforating the thin-film of conducting material with slits and/or holes of desirable shapes, size and pitch in order to enhance wavelength selectivity and/or polarization selectivity.

11. The method of claim 6, wherein the Surface Plasmon Polariton (SPP) “

Light Funnel”

structures are arranged into 1D or 2D arrays, the method additionally comprising;

centrally positioning at least one aperture in a conductor film

surrounding the at least one aperture with symmetrically arranged corrugations on front and back surfaces of the conductor film;

the top view of the pixels comprising a regular shape that can be replicated to completely fill a surface;

interfacing the bottom and top surfaces of the conductor film with insulating materials having significantly different dielectric constants;

positioning the top surface of the conductor film at an image plane of a lens, while the light beam exiting the bottom surface has sub-wavelength cross-section, and very low divergence;

aligning, with high precision, a center of the aperture in each isolated conductor film, to a center of a photo-sensor inside each of the pixels.

12. The method of claim 11, wherein a diameter of the apertures where light is leaked out to the photo-sensors, is much smaller than the wavelength of light, without an occurrence of diffraction, and the diameter of the photo-sensors, fabricated on the top semiconductor film, is identical to the diameter of said apertures plus an additional margin to accommodate a possible misalignment between said apertures and said photo-sensors, resulting from the separate patterning steps for their respective fabrication.

13. The method of claim 12, additionally comprising perforating the conductor film with slits and holes of desirable shapes, size and pitch in order to enhance wavelength selectivity and polarization selectivity.

14. The method of claim 11, additionally comprising perforating the conductor film with slits and/or holes of desirable shapes, size and pitch in order to enhance wavelength selectivity and/or polarization selectivity.

15. The method of claim 11, additionally comprising fabricating the 1D or 2D arrays of the Surface Plasmon Polariton (SPP) “

Light Funnel”

structures on the buried oxide of back-side illuminated TF-SOI or TF-GeOI substrates, with high precision alignment to the devices fabricated on the front-side of the substrates, in particular to the photo-diodes.

16. The method of claim 11, additionally comprising fabricating the 1D or 2D arrays on top of a dielectric layer formed on a last metal layer of a complete metal stack providing interconnects on the front-side of the substrate, suitable for front-side illumination, regardless of substrate type.

17. The method of claim 11 wherein the aperture is a hole.

18. The method of claim 11 wherein the aperture is a slit.

19. The method of claim 1, wherein a back-side structure comprises a monolithically integrated “

Perfect Lens”

or “

Superlens”

planar structure, comprising layers with positive and negative indexes of refraction for the wavelengths of interest, producing image planes aligned with the 1D or 2D arrays of photo-sensors.

20. The method of any of claims 1–

3, 4–

19, 9–

18 wherein the process architecture comprises CMOS image sensors.