Method for making a semiconductor device including band-engineered superlattice using intermediate annealing

• US 7,153,763 B2
• Filed: 05/25/2005
• Issued: 12/26/2006
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: RJ Mears LLC (Atomera Incorporated)
• Inventors: Hytha, Marek, Stephenson, Robert John, Kreps, Scott A.
• Primary Examiner(s): Estrada, Michelle
• Assistant Examiner(s): STARK, JARRETT J
• Application Number:
  US11/136,834
• Publication Number:
  US 20050272239A1
• Time in Patent Office: 580 Days
• Field of Search: 438/400, 438/3, 438/110, 438/240, 438/938, 438/FOR.270, 257/9, 257/E29.298
• US Class Current: 438/604
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization

Abstract

A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include performing at least one anneal prior to completing forming of the superlattice.

Claims

1. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer selected from the group consisting essentially of oxygen, nitrogen, fluorine, and carbon-oxygen constrained within a crystal lattice of adjacent base semiconductor portions, and opposing base semiconductor portions in adjacent groups of layers being chemically bound together; and

performing at least one anneal prior to completing forming of the superlattice.

2. The method according to claim 1 wherein forming the superlattice comprises forming each group by successive deposition of the plurality of base semiconductor monolayers;

and wherein performing the at least one anneal comprises performing the at least one anneal prior to completing the deposition of all of the plurality of base semiconductor monolayers in at least one group of layers.

3. The method according to claim 2 wherein performing the at least one anneal comprises performing the at least one anneal after completing the deposition of at least one of the plurality of base semiconductor monolayers in at least one group of layers.

4. The method according to claim 2 wherein performing the at least one anneal comprises performing the at least one anneal after completing the deposition of no more than eight base semiconductor monolayers.

5. The method according to claim 2 wherein performing the at least one anneal comprises performing the at least one anneal after completing the deposition of no more than four base semiconductor monolayers.

6. The method according to claim 1 wherein performing the at least one anneal comprises performing the at least one anneal at a temperature in a range of about 550 to 750°

C.

7. The method according to claim 1 wherein performing the at least one anneal comprises performing the at least one anneal at a temperature in a range of about 625 to 675°

C.

8. The method according to claim 1 wherein performing the at least one anneal comprises performing the at least one anneal for a time period in a range of about one to thirty minutes.

9. The method according to claim 1 wherein performing the at least one anneal comprises performing the at least one anneal for a time period in a range of about five to fifteen minutes.

10. The method according to claim 1 wherein each at least one non-semiconductor monolayer is a single monolayer thick.

11. The method according to claim 1 wherein each base semiconductor portion is less than eight monolayers thick.

12. The method according to claim 1 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

13. The method according to claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.

14. The method according to claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

15. The method according to claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III–

V semiconductors, and Group II–

VI semiconductors.

16. The method according to claim 1 wherein forming the superlattice comprises forming the superlattice on a substrate.

17. The method according to claim 1 further comprising doping the superlattice with at least one type of conductivity dopant therein.

18. The method according to claim 1 wherein the superlattice defines a channel for the semiconductor device and further comprising:

forming source and drain regions laterally adjacent the superlattice channel; and

forming a gate overlying the superlattice channel.

19. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of successively deposited groups of layers, each group of layers comprising a plurality of successively deposited base silicon monolayers defining a base silicon portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions, and opposing base silicon portions in adjacent groups of layers being chemically bound together; and

performing at least one anneal prior to completing the deposition of all of the plurality of base silicon monolayers in at least one group of layers.

20. The method according to claim 19 wherein performing the at least one anneal comprises performing the at least one anneal after completing the deposition of no more than four base silicon monolayers.

21. The method according to claim 19 wherein performing the at least one anneal comprises performing the at least one anneal at a temperature in a range of about 625 to 675°

C.

22. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, and opposing base silicon portions in adjacent groups of layers being chemically bound to ether; and

performing at least one anneal at a temperature in a range of about 550 to 750°

C. and for a time period in a range of about one to thirty minutes prior to completing forming of the superlattice.

23. The method according to claim 22 wherein forming the superlattice comprises forming each group by successive deposition of the plurality of base silicon monolayers;

and wherein performing the at least one anneal comprises performing the at least one anneal prior to completing the deposition of all of the plurality of base silicon monolayers in at least one group of layers.

24. The method according to claim 22 wherein performing the at least one anneal comprises performing the at least one anneal after completing the deposition of at least one of the plurality of base silicon monolayers in at least one group of layers.

25. The method according to claim 22 wherein performing the at least one anneal comprises performing the at least one anneal after completing the deposition of no more than four base silicon monolayers.

26. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and opposing base semiconductor monolayers in adjacent groups of layers being chemically bound together; and

performing at least one anneal prior to completing forming of the superlattice.

27. The method according to claim 26 wherein forming the superlattice comprises forming each group by successive deposition of the plurality of base semiconductor monolayers;

and wherein performing the at least one anneal comprises performing the at least one anneal prior to completing the deposition of all of the plurality of base semiconductor monolayers in at least one group of layers.

28. The method according to claim 27 wherein performing the at least one anneal comprises performing the at least one anneal after completing the deposition of at least of the plurality of base semiconductor monolayers in at least one group of layers.

29. The method according to claim 27 wherein performing the at least one anneal comprises performing the at least one anneal after completing the deposition of no more than eight base semiconductor monolayers.

30. The method according to claim 27 wherein performing the at least one anneal comprises performing the at least one anneal after completing the deposition of no than four base semiconductor monolayers.

31. The method according to claim 26 wherein performing the at least one anneal comprises performing the at least one anneal at a temperature in a range of about 625 to 675°

C.