Flip chip in leaded molded package and method of manufacture thereof

• US 7,154,168 B2
• Filed: 11/05/2003
• Issued: 12/26/2006
• Est. Priority Date: 12/16/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Joshi, Rajeev, Tangpuz, Consuelo N., Manatad, Romel N.
• Primary Examiner(s): Thai, Luan
• Application Number:
  US10/702,792
• Publication Number:
  US 20050167848A1
• Time in Patent Office: 1,147 Days
• Field of Search: 257/502, 257578-579, 257/673, 257/676, 257737-738, 257778-780, 257/782, 257/787, 257/E23.023, 257/E23.021, 257/E23.031, 257/E23.069
• US Class Current: 257/676
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Claims

1. A semiconductor die package comprising:

a lead frame including a plurality of leads;

a semiconductor die including frontside and a backside, wherein the frontside semiconductor die is coupled to the leadframe using solder; and

a molding compound having a window, the molding compound covering at least a portion of the leadframe and at least a portion of the semiconductor die, wherein the plurality of leads extend out of the molding compound and laterally away from the molding compound, and

wherein the backside of the semiconductor die is exposed through the window and forms an exterior surface of semiconductor die package and is substantially flush with an exterior surface of the molding compound, and

wherein the frontside of the semiconductor die includes a first electrical terminal and the backside of the semiconductor die includes a second electrical terminal.

2. The semiconductor die package of claim 1 wherein the semiconductor die comprises a power transistor.

3. The semiconductor die package of claim 1 wherein ends of the leads are co-planar with the backside of the semiconductor die.

4. The semiconductor die package of claim 1 wherein the semiconductor die package further comprises a second semiconductor die including a second backside, wherein the second semiconductor die is also coupled to the lead frame, and wherein the molding compound has a second window, wherein the second backside is exposed through the second window and forms a second exterior surface of the semiconductor die package and is substantially flush with the exterior surface of the molding compound.

5. The semiconductor die package of claim 4 wherein the lead frame includes a die attach pad, and wherein the first and second semiconductor dies are on the die attach pad.

6. The semiconductor die package of claim 1 wherein the lead frame is pre-plated.

7. The semiconductor die package of claim 6 wherein ends of the leads are co-planar with the backside of the semiconductor die.

8. The semiconductor die package of claim 1 wherein the first electrical terminal is a gate terminal and the second electrical terminal is a drain terminal.

9. The semiconductor die package of claim 8 wherein the surfaces of the leads are substantially coplanar with the backside of the die.

10. The semiconductor die package of claim 8 wherein the leadframe is plated with Ni—

Pd.

11. The semiconductor die package of claim 1 wherein the surfaces of the leads are substantially coplanar with the backside of the die.

12. The semiconductor die package of claim 1 wherein the leadframe is plated with Ni—

Pd.