Isolation buffers with controlled equal time delays
First Claim
1. An apparatus comprising:
- a variable delay isolation buffer having a signal input, a signal output, and a variable delay control input for selectively varying a delay caused by the variable delay isolation buffer in a signal traveling from the signal input to the signal output; and
a delay control circuit having an output providing the variable delay control input of the variable delay isolation buffer, the delay control circuit setting a delay control voltage potential at its output to control delay through the variable delay isolation buffer to substantially match delay through a time delay reference.
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Accused Products
Abstract
A system is provided for controlling the delay in an isolation buffer. Multiple such isolation buffers are used to connect a single signal channel to multiple lines and controlled to provide an equal delay. Isolation buffer delay is controlled to be uniform by varying either power supply voltage or current. A single delay control circuit forming a delay-lock loop supplies the delay control signal to each buffer to assure the uniform delay. Since controlling delay can also vary the output voltage of each isolation buffer, in one embodiment buffers are made from two series inverters: one with a variable delay, and the second without a variable delay providing a fixed output voltage swing. To reduce circuitry needed, in one embodiment an isolation buffer with a variable power supply is provided in a channel prior to a branch, while buffers having a fixed delay are provided in each branch. A wafer test system can be configured using the isolation buffers having equal delays to enable concurrently connecting one tester channel to multiple wafer test probes.
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Citations
14 Claims
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1. An apparatus comprising:
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a variable delay isolation buffer having a signal input, a signal output, and a variable delay control input for selectively varying a delay caused by the variable delay isolation buffer in a signal traveling from the signal input to the signal output; and a delay control circuit having an output providing the variable delay control input of the variable delay isolation buffer, the delay control circuit setting a delay control voltage potential at its output to control delay through the variable delay isolation buffer to substantially match delay through a time delay reference. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus comprising:
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a variable delay isolation buffer having a signal input, a variable delay control input, and an output; and a delay control circuit having an output providing the variable delay control input of the variable delay isolation buffer, the delay control circuit setting a delay control voltage potential at its output to control delay through the variable delay isolation buffer to substantially match delay through a time delay reference, wherein the delay control circuit comprises; a reference delay line; a reference buffer having a signal input, a variable delay control input, and an output; and a phase comparator having a first input connected to reference delay line, a second input connected to the output of the reference buffer, and having an output connected to the variable delay control inputs of the reference buffer and the variable delay isolation buffer. - View Dependent Claims (10, 11, 12, 13, 14)
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Specification