Method and apparatus for compensating amplifier output for temperature and process variations

• US 7,154,329 B2
• Filed: 12/16/2004
• Issued: 12/26/2006
• Est. Priority Date: 12/16/2004
• Status: Expired due to Fees

• Current Assignee: North South Holdings Incorporated (Spherix Incorporated)
• Original Assignee: M/A Com
• Inventors: Douglas, Dale Scott
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US11/013,841
• Publication Number:
  US 20060132230A1
• Time in Patent Office: 740 Days
• Field of Search: 330/2, 330/277, 330/51
• US Class Current: 330/2
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 3/602 Combinations of several amplifiers
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

An amplifier circuit includes a calibration circuit with a controllable circuit element such as a digital resistor. One or more properties of the controllable circuit element (e.g., the resistance in a digital resistor) is varied by a digital calibration word such that the voltage drop across the resistor matches a reference voltage. The calibration word is also used to control the resistance of a transistor that forms a part of a power amplifier to compensate for temperature and process variations. The amplifier may be a switching power amplifier, and the transistor may be a segmented transistor with the width (and hence the channel resistance) controlled by the digital calibration word.

Claims

1. A method for calibrating an output of an amplifier comprising the steps of:

providing an amplifier, the amplifier including a transistor, the transistor having a channel with a digitally controllable channel resistance, the channel resistance changing as a function of a calibration parameter;

generating a calibration word to control a characteristic of a digitally controllable circuit element such that the characteristic remains at a desired level, the circuit element being configured such that the characteristic changes as a function of the calibration parameter in an amount proportional to an amount by which the resistance of the transistor changes as a function of the calibration parameter; and

controlling the channel width of the transistor based on the calibration word such that the resistance of the transistor is calibrated for variations in the calibration parameter.

2. The method of claim 1, wherein the calibration parameter is selected from the group consisting of an operating temperature of the transistor and a fabrication process of the transistor.

3. The method of claim 1, wherein the circuit element is a digital resistor and the characteristic is resistance.

4. The method of claim 1, wherein the amplifier is a switching power amplifier and the transistor includes a segmented transistor.

5. The method of claim 4, wherein the segmented transistor comprises a plurality of FETs and the channel resistance is controlled by controlling a width of the channel of each FET as a function of the calibration word.

6. The method of claim 5, wherein a portion of the width of the segmented transistor is controlled by the calibration word, the portion being less than the entire width of the segmented transistor.

7. The method of claim 6, wherein an entire width of the segmented transistor is controlled by the calibration word.

8. The method of claim 1, wherein the transistor is fabricated using a CMOS process.

9. The method of claim 1, wherein the generating step comprises the steps of:

comparing a reference voltage to a voltage drop across the resistor to generate a comparison value; and

inputting the comparison value to an up/down counter to generating a new count value, the new count value corresponding to the calibration word.

10. An amplifier comprising:

a transistor, the transistor having a channel with a digitally controllable channel resistance, the channel resistance changing as a function of a calibration parameter; and

a calibration circuit including a circuit element having a digitally controllable characteristic that changes as a function of the calibration parameter in an amount proportional to an amount by which the resistance of the transistor changes as a function of the calibration parameter, the calibration circuit being connected to the transistor;

wherein the calibration circuit is configured to generate a calibration word that maintains the characteristic of the circuit element at a desired level over changes in the calibration parameter and to output the calibration word to the transistor to control the channel resistance of the transistor, whereby the channel resistance of the transistor is calibrated for changes in the calibration parameter.

11. The amplifier of claim 10, wherein the calibration parameter is selected from the group consisting of an operating temperature of the transistor and a fabrication process of the transistor.

12. The amplifier of claim 10, wherein the circuit element is a digital resistor and the characteristic is resistance.

13. The amplifier of claim 10, wherein the amplifier is a switching power amplifier and the transistor includes a plurality of segment FET elements.

14. The amplifier of claim 10, wherein the transistor is a segmented transistor comprising a plurality of segment transistors having binary weighted channel widths.

15. The amplifier of claim 10, wherein the transistor is a segmented transistor comprising a plurality of segment transistors having binary weighted channel widths.

16. The amplifier of claim 10, wherein each of the segment transistors is controlled by a corresponding switch under the control of the calibration word.

17. The amplifier of claim 16, wherein each switch comprises a transistor.

18. The amplifier of claim 15, wherein less than all of the segment transistors are controlled by a corresponding switch under the control of the calibration word.

19. The amplifier of claim, 10 wherein the transistor is fabricated using a CMOS process.

20. The amplifier of claim 10, wherein the calibration circuit comprises:

a comparator with a first input connected to the circuit element;

a voltage source connected to a second input of the comparator; and

an up/down counter having an up/down input connected to an output of the comparator and a multiple bit output connected to a control input of the circuit element, the multiple bit output of the counter corresponding to the calibration word.