Liquid crystal display and drive method thereof

• US 7,154,463 B2
• Filed: 07/26/2001
• Issued: 12/26/2006
• Est. Priority Date: 07/27/2000
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwag, Jin-Oh
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): Nguyen, Kevin M.
• Application Number:
  US09/912,523
• Publication Number:
  US 20020015017A1
• Time in Patent Office: 1,979 Days
• Field of Search: 345/53, 345/54, 345/89, 345/92, 345/94, 345/95, 345/96, 345/690, 349/33, 349172-174
• US Class Current: 345/94
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

The present invention provides a liquid crystal display comprising: a liquid crystal panel including a plurality of gate lines, a plurality of data lines perpendicularly intersecting the gate lines, a plurality of liquid crystal capacitors coupled to a previous gate line and having liquid crystals between pixel electrodes and a common electrode, and a plurality of thin film transistors connected to the pixel electrodes of the liquid crystal capacitors; a timing controller receiving image signals and synchronization signals, and generating control signals; a gate driver sequentially applying a stepped-wave pattern gate voltage to a plurality of the gate lines, the stepped-wave pattern gate voltage including a first interval for converting a pixel grayscale level of a subsequent gate line formed in a previous frame to a first gray level, and a second interval for forming a path through which data voltage is applied by controlling the thin film transistors to on; and a data driver for applying a data voltage of a second grayscale level supplied to the liquid crystal capacitors of the liquid crystal panel according to the control signals of the timing controller.

Claims

1. A liquid crystal display (LCD), comprising:

a plurality of gate lines;

a plurality of data lines intersecting the gate lines;

a data driver generating data voltages for the data lines; and

a gate driver generating stepped-wave pattern gate signals for the gate lines, each stepped-wave pattern gate signal including;

a reset interval for converting a grayscale level of a pixel corresponding to a subsequent gate line to an extreme grayscale level;

a gate-on interval following the reset interval; and

an overshoot-interval following the gate-on interval and having the same polarity with a data voltage applied to the pixel.

2. The liquid crystal display of claim 1, wherein the first grayscale level is a black grayscale level when in a normally white mode.

3. The LCD of claim 1, wherein the extreme grayscale level in a normally black mode.

4. A drive method for a liquid crystal display (LCD), comprising:

sequentially applying stepped-wave pattern gate signals to the gate lines, each stepped-wave pattern gate signal comprising;

a reset interval converting a grayscale level of a pixel corresponding to a subsequent gate line to an extreme grayscale level,

a gate-on interval following the reset interval, and

an overshoot interval following the gate-on interval and having the same polarity with a data voltage applied to the pixel; and

applying the data voltage to the pixel.

5. The method of claim 4, wherein the gate signal in the reset interval has the same polarity with the gate signal in the overshoot interval.

6. The method of claim 4, wherein the gate signal in the reset interval has a different polarity from the gate signal in the overshoot interval.

7. The method of claim 4, wherein a voltage level of the gate signal in the overshoot interval is +3V to +10V relative to a gate-off voltage.

8. The method of claim 4, wherein the overshoot interval starts when the gate-on interval ends, and converts to a gate-off voltage when the gate-on interval doubles.

9. The method of claim 4, wherein the extreme grayscale level is a white grayscale level in a normally black mode.

10. The method of claim 4, wherein the extreme grayscale level is a black grayscale level in a normally white mode.

11. The method of claim 4, wherein a voltage level of the gate signal in the reset interval is +3V to +10V relative to a gate-off voltage.

12. The method of claim 4, wherein the reset interval starts about 0.5 μ

s after the gate-on interval starts.

13. A liquid crystal (LCD), comprising:

a gate driver generating a gate signal;

a data driver generating a first data voltage and a second data voltage;

a first gate line transmitting the gate signal;

a second gate line neighboring the first gate line and transmitting the gate signal;

a data line intersecting the first and second gate lines and transmitting the first data signal and the second data signal;

a first switching element connected to the first gate line and the data line and selectively transmitting the first data voltage to a first pixel;

a second switching element connected to the second gate line and the data line and selectively transmitting the second data voltage to a second pixel;

a first liquid crystal capacitance formed at the first pixel;

a second liquid crystal capacitance formed at the second pixel;

a storage capacitance formed between the second liquid crystal capacitance and the first gate line;

wherein the gate signal applied to the first gate line has a first interval having a first voltage converting a grayscale level of the second pixel to an extreme grayscale level, a second interval following the first interval and having a second voltage, a third interval following the second interval and having a third voltage and a fourth interval following the third interval and having a fourth voltage.

14. The LCD of claim 13, wherein the first switching element is turned on by the second voltage and turned off by the fourth voltage.

15. The LCD of claim 14, further comprising a common line providing a common voltage for the first liquid crystal capacitance and the second liquid crystal capacitance,

wherein the third voltage of the gate signal applied to the first gate line is greater than the fourth voltage when the first data voltage is higher than the common voltage, and the third voltage of the gate signal applied to the first gate line is lower than the fourth voltage when the first data voltage is less than the common voltage.

16. The LCD of claim 15, wherein both the first and the third voltages are higher or lower than the fourth voltage.

17. The LCD of claim 16, wherein the liquid crystal display operates in a normally white mode.

18. The LCD of claim 15, wherein one of the first and the third voltages is greater than the fourth voltage and the other is less than the fourth voltage.

19. The LCD of claim 18, wherein the liquid crystal display operates in a normally black mode.

20. The LCD of claim 14, wherein both the first and the third voltages are higher or lower than the fourth voltage.

21. The LCD of claim 20, wherein a level of the third voltage is between levels the first voltage and the fourth voltage.

22. The LCD of claim 14, wherein one of the first and the third voltages is greater than the fourth voltage and the other is less than the fourth voltage.