Memory device capable of stable data writing

• US 7,154,777 B2
• Filed: 08/24/2005
• Issued: 12/26/2006
• Est. Priority Date: 11/27/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Hidaka, Hideto
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US11/209,630
• Publication Number:
  US 20050276111A1
• Time in Patent Office: 489 Days
• Field of Search: 365/173, 365/230.03, 365/189.09
• US Class Current: 365/173
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence

Abstract

A memory device according to the present invention includes a memory cell array including a plurality of memory cells arranged therein, the memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing, and further includes a plurality of current supply sections provided correspondingly to the plurality of regions, respectively. Each of the plurality of current supply sections, when a corresponding region of the plurality of regions is selected as an object for data writing, is activated to supply a data write current to the corresponding region and each of the plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of the plurality of memory cells. The plurality of write select lines are selectively supplied with the data write current from a corresponding one of the plurality of current supply sections.

Claims

1. A non-volatile memory device comprising:

a plurality of memory cells;

a plurality of write current lines provided correspondingly to predetermined units of said plurality of memory cells;

a first wire connected electrically to one end sides of said plurality of write current lines;

a second wire, connected electrically to a first voltage, and connected electrically to at least one of the other end sides of said plurality of write current lines in data writing;

a current supply circuit, in said data writing, activated to connect said first wire electrically to a second voltage and to thereby supply said data write current to said first wire; and

a voltage setting circuit for, when said current supply circuit is in an inactive state, setting said first wire electrically to a third voltage different from said second voltage, wherein

a difference between said first and third voltages is smaller than a difference between said first and second voltages.

2. The non-volatile memory device according to claim 1, wherein

said voltage setting circuit, when power is turned on, connects said first wire electrically to said third voltage till said current supply circuit is activated and, when said current supply circuit enters an inactive state, disconnects said first wire electrically from said third voltage.

3. The non-volatile memory device according to claim 1, wherein

said third voltage is almost equal to said first voltage in level.

4. A non-volatile memory device comprising:

a plurality of memory cells;

a plurality of write current lines provided correspondingly to predetermined units of said plurality of memory cells;

a first wire connected electrically to one end sides of said plurality of write current lines;

a second wire, connected electrically to a first voltage, and connected electrically to at least one of the other end sides of said plurality of write current lines in data writing;

a current supply circuit, in said data writing, activated to connect said first wire electrically to a second voltage and to thereby supply said data write current to said first wire;

an address decode circuit for, in said data writing, selecting a write current line to receive supply of said data write current from said plurality of write current lines; and

a voltage setting circuit for setting said first wire electrically to a third voltage different from said second voltage during a predetermined period from the start of data writing till said data write current is supplied into said write current line selected by said address decode circuit, wherein

a difference between said first and third voltages is smaller than a difference between said first and second voltages.

5. The non-volatile memory device according to claim 4, wherein

said predetermined period is determined according to a time required by said address decode circuit for selection of said write current line.

6. The non-volatile memory device according to claim 4, wherein

said voltage setting circuit includes:

a dummy write current line designed and arranged in a similar way to the way that said plurality of write current lines are designed and arranged; and

a switch connecting said third voltage electrically to said dummy write current line during said predetermined period, and

said dummy write current line is connected electrically to said first wire.

7. The non-volatile memory device according to claim 4, wherein

each of said plurality of memory cells includes:

a first magnetic layer having a fixed magnetic direction;

a second magnetic layer magnetized in a direction corresponding to a magnetic field generated by said data write current controlled according to a level of write data; and

an insulating film formed between said first and second magnetic layers.