Data recovery system and applications thereof in radio receivers

• US 7,154,974 B2
• Filed: 02/12/2002
• Issued: 12/26/2006
• Est. Priority Date: 02/12/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ibrahim, Brima, Jensen, Henrik
• Primary Examiner(s): Kim, Kevin
• Application Number:
  US10/074,294
• Publication Number:
  US 20030161413A1
• Time in Patent Office: 1,778 Days
• Field of Search: 375/355, 375/317
• US Class Current: 375/355
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes

Abstract

A method and apparatus for data recovery includes processing that begins by receiving an encoded signal at a transmit symbol rate. Such an encoded signal includes data that is represented by positive and negative pulses. The processing continues by determining at least one reference crossing of the encoded signal (e.g., detecting a 0 crossing). The processing then continues by determining a sampling phase of a system symbol rate based on the reference crossing. The processing then continues by sampling the encoded signal at the determined sampling phase with respect to the system symbol rate to recapture the data.

Claims

1. A method for data recovery, the method comprises:

receiving an encoded signal at a transmit symbol rate, wherein the encoded signal includes first data values having a positive sign with respect to a reference and second data values having a negative sign with respect to the reference;

determining at least one reference crossing of the encoded signal;

determining a sampling phase based on the at least one reference crossing and a system symbol rate to produce a determined sampling phase, wherein the determining the sampling phase includes;

setting an initial sampling phase with respect to the system symbol rate;

setting an accumulator to a mid point value; and

utilizing the initial sampling phase as the determined sample phase when the encoded signal is initially detected;

updating the determined sampling phase based on at least one of an overflow of the accumulator and an underflow of the accumulator; and

sampling the encoded signal at the updated determined sampling phase with respect to the system symbol rate to recapture data from the encoded signal.

2. The method of claim 1, wherein the receiving the encoded signal further comprises:

receiving a multi-level encoded signal at the transmit symbol rate, wherein the multi-level encoded signal includes the first data values at a first magnitude having the positive sign with respect to the reference, third data values at a second magnitude having the positive sign with respect to the reference, the second data values at the first magnitude having the negative sign with respect to the reference, and fourth data values at the second magnitude having the negative sign with respect to the reference.

3. The method of claim 1, wherein the receiving the encoded signal further comprises:

receiving a DC offset encoded signal;

determining a DC offset; and

substantially removing the DC offset from the DC encoded signal to produce the encoded signal.

4. The method of claim 1 further comprises:

determining the system symbol rate as one of a plurality of system symbol rates based on the encoded data.

5. The method of claim 1, wherein the updating the determined sampling phase further comprises:

for a current reference crossing of the at least one reference crossing, determining a corresponding current sampling phase;

comparing the determined sampling phase to the corresponding current sampling phase;

when the comparison of the determined sampling phase to the corresponding current sampling phase is unfavorable, adjusting the accumulator;

determining whether the accumulator has overflowed or underflowed; and

when the accumulator has overflowed or underflowed, adjusting the determined sampling phase.

6. The method of claim 5 further comprises:

determining the comparison of the determined sampling phase to the corresponding current sampling phase to be unfavorable when the corresponding current sampling phase is greater than the determined sampling phase;

incrementing the accumulator when the corresponding current sampling phase is greater than the determined sampling phase;

when the accumulator has overflowed, increasing the determined sampling phase by a sampling phase delta value; and

resetting the accumulator to a mid-point value.

7. The method of claim 5 further comprises:

determining the comparison of the determined sampling phase Lo the corresponding current sampling phase to be unfavorable when the corresponding current sampling phase is less than the determined sampling phase;

decrementing the accumulator when the corresponding current sampling phase is less than the determined sampling phase;

when the accumulator has underflowed, decreasing the determined sampling phase by a sampling phase delta value; and

resetting the accumulator to a mid-point value.

8. The method of claim 5 further comprises:

determining whether the encoded signal is being received during in acquisition mode or in a tracking mode;

when the encoded signal is being received during the acquisition mode;

initializing the accumulator to a mid point value of two, wherein the accumulator has a range of zero to four;

when the accumulator overflows or underflows, adjusting the determined sampling phase by a sampling phase delta value of two;

when the encoded signal is being received during the tracking mode;

initializing the accumulator to a mid point value of sixteen, wherein the accumulator has a range of zero to thirty-two;

when the accumulator overflows or underflows, adjusting the determined sampling phase by a sampling phase delta value of one.

9. The method of claim 1, wherein the determining the sampling phase further comprises:

determining sampling time of the sampling phase based on time of the at least one reference crossing less one-half of symbol time of the system symbol rate, wherein the symbol time includes a plurality of oversampling times, wherein the plurality of oversampling times corresponds to a plurality of sampling phases that includes the determined sampling phase.

10. A data recovery module comprises:

processing module; and

memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to;

receive an encoded signal at a transmit symbol rate, wherein the encoded signal includes first data values having a positive sign with respect to a reference and second data values having a negative sign with respect to the reference;

determine at least one reference crossing of the encoded signal;

determine a sampling phase based on the at least one reference crossing and a system symbol rate to produce a determined sampling phase;

for a current reference crossing of the at least one reference crossing, determining a corresponding current sampling phase;

comparing the determined sampling phase to the corresponding current sampling phase;

when the comparison of the determined sampling phase to the corresponding current sampling phase is unfavorable, adjusting an accumulator;

updating the determined sampling phase based on a value of the accumulator; and

sample the encoded signal at the updated determined sampling phase with respect to the system symbol rate to recapture data from the encoded signal.

11. The data recovery module of claim 10, wherein the memory further comprises operational instructions that cause the processing module to receive the encoded signal by:

receiving a DC offset encoded signal;

determining a DC offset; and

substantially removing the DC offset from the DC encoded signal to produce the encoded signal.

12. The data recovery module of claim 10, wherein the memory further comprises operational instructions that cause the processing module to:

determine the system symbol rate as one of a plurality of system symbol rates based on the encoded data.

13. The data recovery module of claim 10, wherein the memory further comprises operational instructions that cause the processing module to determine the sampling phase by:

setting an initial sampling phase with respect to the system symbol rate;

setting the accumulator to a mid point value; and

utilizing the initial sampling phase as the determined sample phase when the encoded signal is initially detected.

14. The data recovery module of claim 10, wherein the memory further comprises operational instructions that cause the processing module to update the determined sampling phase by:

determining whether the accumulator has overflowed or underflowed; and

when the accumulator has overflowed or underflowed, adjusting the determined sampling phase.

15. The data recovery module of claim 14, wherein the memory further comprises operational instructions that cause the processing module to:

determine the comparison of the determined sampling phase to the corresponding current sampling phase to be unfavorable when the corresponding current sampling phase is greater than the determined sampling phase;

increment the accumulator when the corresponding current sampling phase is greater than the determined sampling phase;

when the accumulator has overflowed, increase the determined sampling phase by a sampling phase delta value; and

reset the accumulator to a mid-point value.

16. The data recovery module of claim 14, wherein the memory further comprises operational instructions that cause the processing module to:

determine the comparison of the determined sampling phase to the corresponding current sampling phase to be unfavorable when the corresponding current sampling phase is less than the determined sampling phase;

decrement the accumulator when the corresponding current sampling phase is less than the determined sampling phase;

when the accumulator has underflowed, decrease the determined sampling phase by a sampling phase delta value; and

reset the accumulator to a mid-point value.

17. The data recovery module of claim 14, wherein the memory further comprises operational instructions that cause the processing module to:

determine whether the encoded signal is being received during in acquisition mode or in a tracking mode;

when the encoded signal is being received during the acquisition mode;

initialize the accumulator to a mid point value of two, wherein the accumulator has a range of zero to four;

when the accumulator overflows or underflows, adjust the determined sampling phase by a sampling phase delta value of two;

when the encoded signal is being received during the tracking mode;

initialize the accumulator to a mid point value of sixteen, wherein the accumulator has a range of zero to thirty-two;

when the accumulator overflows or underflows, adjust the determined sampling phase by a sampling phase delta value of one.

18. The data recovery module of claim 10, wherein the memory further comprises operational instructions that cause the processing module to determine the sampling phase by:

determining sampling time of the sampling phase based on time of the at least one reference crossing less one-half of symbol time of the system symbol rate, wherein the symbol time includes a plurality of oversampling times, wherein the plurality of oversampling times corresponds to a plurality of sampling phases that includes the determined sampling phase.

19. A radio receiver comprises:

low noise amplifier operably coupled to amplify a radio frequency (RF) signal to produce an amplified RF signal;

frequency step-down section operably coupled to step-down frequency of the amplified RF signal to provide an intermediate frequency signal;

bandpass filter operably coupled to pass frequency components of the intermediate frequency signal in a bandpass range and to substantially attenuate frequency components of the intermediate frequency signal outside of the bandpass range to produce a filtered signal;

analog to digital converter operably coupled to convert the filtered signal into a digital signal;

digital intermediate frequency demodulator operably coupled to demodulate the digital signal to produce a demodulated signal; and

data and timing recovery module operably coupled to recapture data from the demodulated signal, wherein the data and timing recovery module includes;

DC offset estimation module to generate a DC offset from the demodulated signal;

subtraction module operably coupled to subtract the DC offset from the demodulated data to produce an encoded signal; and

timing recovery module operably coupled to sample the encoded signal at a determined sampling phase with respect to a system symbol rate to produce the recaptured data, wherein the timing recovery module determines the determined sampling phased based on at least one reference crossing of the encoded signal determining a current sampling phase based on a current reference crossing of the encoded signal, comparing the determined sampling phase to the current sampling phase, when the comparison of the determined sampling phase to the corresponding current sampling phase is unfavorable, adjusting an accumulator, and updates the determined sampling phase based on a value of the accumulator.

20. The radio receiver of claim 19, wherein the timing recovery module further comprises:

processing module; and

memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to;

determine the system symbol rate as one of a plurality of system symbol rates based on the encoded data.

21. The radio receiver of claim 20, wherein the memory further comprises operational instructions that cause the processing module to determine the sampling phase by:

setting an initial sampling phase with respect to the system symbol rate;

setting the accumulator to a mid point value; and

utilizing the initial sampling phase as the determined sample phase when the encoded signal is initially detected.

22. The radio receiver of claim 20, wherein the memory further comprises operational instructions that cause the processing module to update the determined sampling phase by:

determining whether the accumulator has overflowed or underflowed; and

when the accumulator has overflowed or underflowed, adjusting the determined sampling phase.

23. The radio receiver of claim 22, wherein the memory further comprises operational instructions that cause the processing module to:

determine the comparison of the determined sampling phase to the corresponding current sampling phase to be unfavorable when the corresponding current sampling phase is greater than the determined sampling phase;

increment the accumulator when the corresponding current sampling phase is greater than the determined sampling phase;

when the accumulator has overflowed, increase the determined sampling phase by a sampling phase delta value; and

reset the accumulator to a mid-point value.

24. The radio receiver of claim 22, wherein the memory further comprises operational instructions that cause the processing module to:

determine the comparison of the determined sampling phase to the corresponding current sampling phase to be unfavorable when the corresponding current sampling phase is less than the determined sampling phase;

decrement the accumulator when the corresponding current sampling phase is less than the determined sampling phase;

when the accumulator has underflowed, decrease the determined sampling phase by a sampling phase delta value; and

reset the accumulator to a mid-point value.

25. The radio receiver of claim 22, wherein the memory further comprises operational instructions that cause the processing module to:

determine whether the encoded signal is being received during in acquisition mode or in a tracking mode;

when the encoded signal is being received during the acquisition mode;

initialize the accumulator to a mid point value of two, wherein the accumulator has a range of zero to four;

when the accumulator overflows or underflows, adjust the determined sampling phase by a sampling phase delta value of two;

when the encoded signal is being received during the tracking mode;

initialize the accumulator to a mid point value of sixteen, wherein the accumulator has a range of zero to thirty-two;

when the accumulator overflows or underflows, adjust the determined sampling phase by a sampling phase delta value of one.

26. The radio receiver of claim 20, wherein the memory further comprises operational instructions that cause the processing module to determine the sampling phase by:

determining sampling time of the sampling phase based on time of the at least one reference crossing less one-half of symbol time of the system symbol rate, wherein the symbol time includes a plurality of oversampling times, wherein the plurality of oversampling times corresponds to a plurality of sampling phases that includes the determined sampling phase.