Frequency controller

• US 7,154,976 B2
• Filed: 08/29/2002
• Issued: 12/26/2006
• Est. Priority Date: 08/29/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Williams, Kalvin
• Primary Examiner(s): Natnael, Paulos M.
• Application Number:
  US10/230,565
• Publication Number:
  US 20040041947A1
• Time in Patent Office: 1,580 Days
• Field of Search: 348536-538, 348/54, 327156-159, 375/371, 375/373, 375334-336, 324/76.24, 331/11
• US Class Current: 375/371
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• CPC Class Codes: H04N 21/2389 Multiplex stream processing, e.g. multiplex stream encrypting
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4385 Multiplex stream processing, e.g. multiplex stream decrypting
• CPC Class Codes: H04N 5/50 Tuning indicators; Automatic tuning control

Abstract

The invention may relate to a digital frequency adjuster for adjusting a first frequency of a first signal. The digital frequency adjuster may comprise a first digital delay line and a first control circuit. The first digital delay line may comprise a plurality of taps. The first digital delay line may be configured to (i) receive the first signal and (ii) generate a second signal. The first control circuit may be configured to control dynamic assertion of respective ones of the taps at a rate such that the second signal has a second frequency different from the first frequency of the first signal.

Claims

1. A digital frequency adjuster for adjusting a first frequency of a first signal, the digital frequency adjuster comprising:

a first digital delay line comprising a plurality of taps arranged as inputs, wherein said first digital delay line is configured to (i) receive said first signal and (ii) generate a second signal; and

a first control circuit configured to control dynamic assertion of respective ones of said taps at a rate such that said second signal has (i) in a first condition said first frequency and (ii) in a second condition a second frequency different from said first frequency of said first signal.

2. The digital frequency adjuster according to claim 1, wherein said first digital delay line has an aggregate delay length at least as long as a repetition period of said first signal.

3. The digital frequency adjuster according to claim 1, wherein in said second condition said first control circuit is further configured to periodically assert respective ones of said taps to periodically reduce a delay of said first digital delay line, thereby to cause said second frequency of said second signal to be higher than said first frequency of said first signal.

4. The digital frequency adjuster according to claim 1, wherein in said second condition said first control circuit is further configured to periodically assert respective ones of said taps to periodically increase a delay of said first digital delay line, thereby to cause said second frequency of said second signal to be lower than said first frequency of said first signal.

5. The digital frequency adjuster according to claim 1, wherein said first control circuit is further configured to assert said taps cyclically.

10. The digital frequency adjuster according to claim 1, wherein said first control circuit comprises a state machine defining a state transition function.

11. The digital frequency adjuster according to claim 1, further comprising a second control circuit configured to (i) process said second signal and (ii) generate an adjustment control signal for controlling said first control circuit to synchronize said second frequency of said second signal to a reference signal.

13. The digital frequency adjuster according to claim 1, further comprising a calibration circuit configured to generate a third signal for determining at least one of (i) a first wrap position of said taps and (ii) a second wrap position of said taps.

14. The digital frequency adjuster according to claim 13, wherein said calibration circuit comprises:

a second digital delay line comprising a plurality of second taps arranged as inputs; and

a second control circuit configured to selectively assert respective ones of said second taps for determining which of said second taps corresponds to a delay approximately equal to a repetition period of said first signal.

15. The digital frequency adjuster according to claim 1, wherein said digital frequency adjuster is implemented in an integrated circuit.

16. The digital frequency adjuster according to claim 1, wherein said digital frequency adjuster is implemented in a processor for processing a digital television signal, and said digital frequency adjuster is configured to generate said second signal synchronized to a reference frequency of a program clock reference in said digital television signal.

6. A digital frequency adjuster for adjusting a first frequency of a first signal, the digital frequency adjuster comprising:

a first digital delay line comprising a plurality of taps and configured to (i) receive said first signal and (ii) generate a second signal; and

a first control circuit configured to control dynamic assertion of respective ones of said taps at a rate such that said second signal has a second frequency different from said first frequency of said first signal, wherein said taps include a first wrap position and a second wrap position.

7. The digital frequency adjuster according to claim 6, wherein a length of an aggregate delay between said first wrap position and said second wrap position is approximately an integer multiple of a repetition period of said first signal.

8. The digital frequency adjuster according to claim 6, wherein said first control circuit is further configured to assert said taps in a sequence of:

said first wrap position;

a no tap position; and

said second wrap position.

9. The digital frequency adjuster according to claim 6, wherein said first control circuit is further configured to assert said taps in a sequence of:

said second wrap position;

both said first wrap position and said second wrap position; and

said first wrap position.

21. The digital frequency adjuster according to claim 6, wherein said first control circuit is further configured to periodically assert respective ones of said taps to wrap a delay of said first digital delay line between said first wrap position and said second wrap position.

12. A digital frequency adjuster for adjusting a first frequency of a first signal, the digital frequency adjuster comprising:

a first digital delay line comprising a plurality of taps and configured to (i) receive said first signal and (ii) generate a second signal;

a first control circuit configured to control dynamic assertion of respective ones of said taps at a rate such that said second signal has a second frequency different from said first frequency of said first signal; and

a counter clocked by said second signal.

22. The digital frequency adjuster according to claim 12, further comprising a processor generating an adjustment control signal to synchronize a first count rate of said counter to a second count rate from a reference signal.

17. A circuit for generating multiple, independently adjustable, clock frequencies from a reference signal having a reference frequency, the circuit comprising:

a first frequency adjuster configured to generate a first signal having a first frequency from said reference signal, said first frequency adjuster comprising;

a first digital delay line comprising a plurality of first taps and configured to (i) receive said reference signal and (ii) generate said first signal; and

a first control circuit configured to control said first taps of said first digital delay line for controlling said first frequency of said first signal; and

a second frequency adjuster configured to generate a second signal having a second frequency from said reference signal, said second frequency adjuster comprising;

a second digital delay line comprising a plurality of second taps and configured to Ci) receive said reference signal and (ii) generate said second signal; and

a second control circuit configured to control said second taps of said second digital delay line for controlling said second frequency of said second signal.

18. The circuit according to claim 17, wherein said circuit is implemented in a processor for processing multiple digital television channel signals, said first frequency of said first signal being synchronizable to a first program clock reference of a first digital television signal channel, and said second frequency of said second signal being synchronizable to a second program clock reference of a second digital television signal channel.

19. A method of adjusting a first frequency of a first signal, the method comprising the steps of:

(A) receiving said first signal by a digital delay line comprising a plurality of delay taps arranged as inputs;

(B) generating a second signal from said digital delay line; and

(C) controlling respective ones of said delay taps at a rate such that said second signal has (i) in a first condition said first frequency and (ii) in a second condition a second frequency different from said first frequency of said first signal.

20. A digital frequency adjuster for adjusting a first frequency of a first signal, comprising:

means for (i) receiving said first signal, (ii) receiving a control signal at a plurality of delay taps arranged as inputs and (iii) generating a second signal; and

means for controlling respective bits of said control signal at a rate such that said second signal has a second frequency different from said first frequency of said first signal.