Timing recovery with variable bandwidth phase locked loop and non-linear control paths
First Claim
1. A method of enhancing jitter tolerance in a communications network, comprising:
- providing at least two non-linear paths, a first of said non-linear paths to adjust a phase of an input data in response to a data pattern of said input data, and a second of said non-linear paths to adjust said phase of said input data in response to an amplitude of data samples from said input data, and a phase locked loop to lock a phase of a clock to said phase of said input data;
inputting said input data to said communications network;
estimating a phase error based on said data samples from both a center of a data eye of said input data and from a phase sample from said input data half-a-baud later in time, said data samples and said phase sample being derived from said input data;
correlating said phase error with a sign of recovered data to provide a correlated phase error, the sign being a positive or negative value;
filtering said correlated phase error by a loop filter to generate an output;
summing said output with output from said at least two non-linear paths to generate a summed output; and
converting said summed output into clock phase information.
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Accused Products
Abstract
A timing recovery system includes a phase locked loop with a variable bandwidth loop filter, several data dependent gain units, and three proportional paths with non-linear control. The system provides excellent jitter tolerance with a wide variation in data density and large amplitude jitter with a wide frequency range. The gain of both an included loop filter and a phase detector may be varied with both frequency and data density. Direct, unfiltered adjustments may be made to phase based on a received data pattern and phase error magnitude to reduce loop latency and provide temporary and immediate boost in the loop gain of the phase locked loop. Direct, unfiltered adjustments may also be made to phase based on the sign of the first differential of an accumulator output during long strings of zeros to help maintain tracking even with a very low data density.
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Citations
23 Claims
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1. A method of enhancing jitter tolerance in a communications network, comprising:
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providing at least two non-linear paths, a first of said non-linear paths to adjust a phase of an input data in response to a data pattern of said input data, and a second of said non-linear paths to adjust said phase of said input data in response to an amplitude of data samples from said input data, and a phase locked loop to lock a phase of a clock to said phase of said input data; inputting said input data to said communications network; estimating a phase error based on said data samples from both a center of a data eye of said input data and from a phase sample from said input data half-a-baud later in time, said data samples and said phase sample being derived from said input data; correlating said phase error with a sign of recovered data to provide a correlated phase error, the sign being a positive or negative value; filtering said correlated phase error by a loop filter to generate an output; summing said output with output from said at least two non-linear paths to generate a summed output; and converting said summed output into clock phase information. - View Dependent Claims (2, 3, 4)
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5. A timing recovery system to receive input data having a phase, comprising:
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a phase locked loop to lock a phase of a clock to the phase of said input data, said phase locked loop receiving said input data and generating a phase locked loop output, wherein said phase locked loop includes; a phase detector to determine said phase of said input data, said phase detector receiving said input data and generating a phase detector output; and a loop filter to provide an additional frequency characteristic to said phase detector output, said loop filter receiving said phase detector output and generating said phase locked loop output; a first proportional path with non-linear control to adjust the phase of said input data in response to a data pattern of said input data, said first proportional path receiving said input data and generating a first proportional path output; a second proportional path with non-linear control to adjust the phase of said input data in response to an amplitude of data samples derived from said input data, said second proportional path receiving said input data and generating a second proportional path output; a system summing node, wherein said phase locked loop output, said first proportional path output, and said second proportional path output are summed by said system summing node to generate a system summing node output; a data density detector to monitor a density of said input data, said data density detector receiving said input data and generating a data density detector output; and a frequency detector to determine a frequency of an incoming timing jitter of said input data, said frequency detector receiving said phase detector output and generating a frequency detector output. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A receiver system for receiving input data having a phase, said receiver system comprising:
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a receiver circuit; an antenna in electronic communication with said receiver circuit; and a timing recovery system circuit in electronic communication with said receiver circuit, said timing recovery system circuit comprising; a phase locked loop to lock a phase of a local clock to the phase of said input data, said phase locked loop receiving said input data and generating a phase locked loop output, wherein said phase locked loop further includes; a phase detector to determine said phase of said input data, said phase detector receiving said input data and generating a phase detector output, and a loop filter to provide an additional frequency characteristic to said phase detector output, said loop filter receiving said phase detector output and generating said phase locked loop output; a first proportional path with non-linear control to adjust the phase of said input data in response to a data pattern of said input data, said first proportional path receiving said input data and generating a first proportional path output; a second proportional path with non-linear control to adjust the phase of said input data in response to an amplitude of data samples derived from said input data, said second proportional path receiving said input data and generating a second proportional path output; and a system summing node, wherein said phase locked loop output, said first proportional path output, and said second proportional path output are summed by said system summing node to generate a system summing node output; and a data density detector to monitor a density of said input data, said data density detector receiving said input data and generating a data density detector output; and a frequency detector to determine a frequency of an incoming timing jitter of said input data, said frequency detector receiving said phase detector output and generating a frequency detector output. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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Specification