CRC calculation for data with dynamic header

• US 7,155,658 B2
• Filed: 12/20/2002
• Issued: 12/26/2006
• Est. Priority Date: 12/20/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Huffman, Amber D., Grimsrud, Knut S.
• Primary Examiner(s): CHUNG, PHUNG M
• Application Number:
  US10/327,396
• Publication Number:
  US 20040123221A1
• Time in Patent Office: 1,467 Days
• Field of Search: 714/776, 714/781, 714/758
• US Class Current: 714/776
• CPC Class Codes: H03M 13/093 CRC update after modification of the information word

Abstract

A method for performing CRC calculations on packets with dynamic headers is disclosed. The header may be changed during transmission across a network. When the header is changed, a CRC associated with the header is recalculated such that a residue of the initial seed value is always obtained. A final CRC covers the entire packet including the header and its header CRC, or just the data portion of the packet. The final CRC remains valid and unchanged during transmission of the packet, allowing an endpoint along the network to confirm the validity of the entire packet. By only changing the CRC associated with the changed portion of the packet (the header CRC), the introduction of errors during transmission of the packet is minimized.

Claims

1. A transmission interface, comprising:

a packet to be transmitted across the transmission interface, the packet comprising a header, a first cyclic redundancy check associated with the header, a data portion, and a second cyclic redundancy check; and

a device for transmitting the packet across the transmission interface, the device including an engine for computing cyclic redundancy checks, wherein the device;

generates the first cyclic redundancy check by;

initializing the engine with a seed;

performing a first modular arithmetic operation on the header of the packet, using a generator polynomial, to produce a residue; and

performing a second modular arithmetic operation on the residue using a header polynomial.

2. The transmission interface of claim 1, wherein the device further:

performs the first modular arithmetic operation on the data portion, using the generator polynomial, to compute the second cyclic redundancy check.

3. The transmission interface of claim 2, wherein the engine is not re-initialized with a new seed between generating the first cyclic redundancy check and the second cyclic redundancy check.

4. The transmission interface of claim 3, further comprising

a third device for receiving the packet across the transmission interface, wherein the third device verifies an error-free transmission of the data by:

initializing a third engine with the seed;

obtaining a second portion of the packet into the third engine, the second portion comprising the header, the first cyclic redundancy check, the data portion, and the second cyclic redundancy check;

performing the first modular arithmetic operation on the second portion using the generator polynomial, to produce a third residue;

wherein the third residue is an expected result.

5. The transmission interface of claim 4, wherein the engine, the second engine, and the third engine are identical.

6. The transmission interface of claim 4, wherein the engine, the second engine, and the third engine comprise hardware circuitry.

7. The transmission interface of claim 4, wherein the engine, the second engine, and the third engine comprise software programs.

8. The transmission interface of claim 4, wherein the engine, the second engine, and the third engine comprise a combination of hardware circuitry and software programs.

9. The transmission interface of claim 4, wherein the device is a host port, the second device is a router, and the third device is a receiving device.

10. The transmission interface of claim 4, wherein the modulus in the first and second modular arithmetic operations are prime numbers.

11. The transmission interface of claim 10, wherein the first modular arithmetic operation is a modulo-2 operation and the second modular arithmetic operation is an exclusive OR operation.

12. The method of claim 11, further comprising:

identifying a change to the dynamic portion to a new dynamic portion;

generating a fourth cyclic redundancy check value for the new dynamic portion;

transmitting the packet comprising the new dynamic portion across the interface to a receiving device;

receiving a third packet portion comprising the new dynamic portion and the fourth cyclic redundancy check; and

generating a fifth cyclic redundancy check of the third packet portion to produce a third residue;

wherein the third residue equals the seed following error-free transmission of the packet across the interface.

13. The transmission interface of claim 3, further comprising:

a third device for receiving the packet across the transmission interface, wherein the third device verifies an error-free transmission of the data by;

initializing a third engine with the seed;

obtaining a second portion of the packet into the third engine, the second portion comprising the data portion and the second cyclic redundancy check;

performing the first modular arithmetic operation on the second portion using the generator polynomial, to produce a third residue;

wherein the third residue is an expected result.

14. The transmission interface of claim 2, further comprising:

a second device for receiving the packet across the transmission interface, wherein the second device verifies an error-free transmission of the header by;

Initializing a second engine with the seed;

obtaining a portion of the packet into the second engine, the portion comprising the header and the first cyclic redundancy check;

performing the first modular arithmetic operation on the portion using the generator polynomial, to produce a second residue;

wherein the second residue equals the seed.

15. The transmission interface of claim 1, wherein the seed is 0×

52325032 and the header polynomial is 0×

F1F21904.

16. A method, comprising:

generating a first cyclic redundancy check of a dynamic portion of a packet using a seed;

generating a second cyclic redundancy check of a static portion of the packet;

transmitting the packet across an interface to a receiving device;

receiving a packet portion comprising the dynamic portion and the first cyclic redundancy check; and

generating a third cyclic redundancy check of the packet portion to produce a first residue;

wherein the first residue equals the seed following error-free transmission of the packet across the interface.

17. The method of claim 16, generating the first cyclic redundancy check value further comprising:

initializing an engine with the seed;

performing a first modular arithmetic operation on the dynamic portion of the packet using a generator polynomial, to produce a second residue, wherein a first modulus of the first modular arithmetic operation is a prime number; and

performing a second modular arithmetic operation on the second residue using a header polynomial, wherein a second modulus of the second modular arithmetic operation is a prime number.

18. The method of claim 16, generating the second cyclic redundancy check value further comprising:

performing the first modular arithmetic operation on a second packet portion using the generator polynomial, the second packet portion comprising the dynamic portion, the first cyclic redundancy check value, and the static portion of the packet.

19. A system comprising:

an engine initialized using a seed, wherein the engine performs modular arithmetic on incoming packets using a generator polynomial;

a host port comprising the engine, wherein the host port engine;

generates a first cyclic redundancy check for a first portion of the packet; and

generates a second cyclic redundancy check for a second portion of the packet; and

a router comprising the engine, wherein the router is remote from the host port and the host port transmits packets to the router, wherein the router engine;

performs modular arithmetic on the first cyclic redundancy check and the first portion to produce a residue equal to the seed where the packet is transmitted without error.

20. The system of claim 19, further comprising:

a receiving device comprising the engine, wherein the receiving device is remote from the host port, wherein the receiving device engine;

performs modular arithmetic on the second cyclic redundancy check and the second portion to produce a residue equal to an expected result where the packet is transmitted without error.

21. The system of claim 19, further comprising:

a receiving device comprising the engine, wherein the receiving device is remote from the host port, wherein the receiving device engine;

performs modular arithmetic on the first portion, the first cyclic redundancy check, the second cyclic redundancy check, and the second portion to produce a residue equal to an expected result where the packet is transmitted without error.

22. The system of claim 19, further comprising:

a receiving device comprising the engine, wherein the receiving device is remote from the host port, wherein the receiving device engine;

performs modular arithmetic on either a first collection comprising the first portion, the first cyclic redundancy check, the second cyclic redundancy check, and the second portion, or a second collection comprising the second cyclic redundancy check and the second portion, wherein the residue produced by the receiving device is identical whether performed on the first collection or the second collection.