Design-manufacturing interface via a unified model

• US 7,155,689 B2
• Filed: 10/07/2003
• Issued: 12/26/2006
• Est. Priority Date: 10/07/2003
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Magma Design Automation (Synopsys Incorporated)
• Inventors: Pierrat, Christophe, Wong, Alfred K.
• Primary Examiner(s): Garbowski, Leigh M.
• Application Number:
  US10/680,592
• Publication Number:
  US 20050076316A1
• Time in Patent Office: 1,176 Days
• Field of Search: None
• US Class Current: 716/52
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have adverse impact on all parts of the integrated circuit creation flow where design rules are used. In addition, segregation of the various layout data modification steps required for deep sub-micrometer manufacturing are resulting in slack and inefficiencies. This invention describes methods to improve integrated circuit creation via the use of a unified model of fabrication processes and circuit elements that can complement or replace design rules. By capturing the interdependence among fabrication processes and circuit elements, the unified model enables efficient layout generation, resulting in better integrated circuits.

Claims

1. A method for obtaining a layout description for a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a layout of said target patterned layer;

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; and

computing a description of a portion of said layout using said first parametric representation and said second parametric representation.

2. The method of claim 1, wherein said computing includes determining effects due to placement fluctuations, process variations, or a combination of both.

3. The method of claim 1, wherein said model is based on one of the following:

physical theory, approximations, heuristics, or any combination thereof.

4. The method of claim 1, wherein said description includes one of the following:

a physical description, an electrical description, or a combination of both.

5. The method of claim 1, wherein at least one of said parametric representations is one of the following parametric representations of:

a lithography process, a mask-making process, an oxidation process, a deposition process, an etching process, an epitaxy process, an ion implantation process, a thermal process, a chemical-mechanical polishing process, a transistor, a capacitor, an inductor, or a resistor.

6. The method of claim 1, wherein said computing includes decomposition of said layout.

7. The method of claim 1, wherein said computing includes modification of said layout.

8. The method of claim 1, wherein said computing includes identification of a circuit element with said layout.

9. The method of claim 8, wherein said identification includes identification based on a physical description computed by said model.

10. A method for verifying a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a layout of said target patterned layer;

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one the the plurality of patterned layers other than the target patterned layer;

computing a target description of a portion of said layout using said target patterned layer of material;

computing a description of a portion of said layout using said first parametric representation and said second parametric representation; and

comparing said description with said target description.

11. The method of claim 10, wherein said computing a description includes determining effects due to placement fluctuations, process variations, or a combination of both.

12. The method of claim 10, wherein said description is checked against a design rule defined by the manufacturing and electrical requirements of said integrated circuit.

13. The method of claim 10, wherein said model is based on one of the following:

physical theory, approximations, heuristics, or any combination thereof.

14. The method of claim 10, wherein at least one of said parametric representations is one of the following parametric representations of:

a lithography process, a mask-making process, an oxidation process, a deposition process, an etching process, an epitaxy process, an ion implantation process, a thermal process, a chemical-mechanical polishing process, a transistor, a capacitor, an inductor, or a resistor.

15. The method of claim 10, wherein said computing a description includes:

modifying said layout to obtain a modified layout; and

computing said description from said modified layout.

16. The method of claim 15, wherein said modifying includes one of the following:

dummy fill insertion, phase-shifting conversion, optical proximity correction, or any combination thereof.

17. The method of claim 10, wherein said computing a description includes:

identifying a circuit element with said layout; and

obtaining said description from said circuit element.

18. The method of claim 17, wherein said identifying comprises:

decomposing said layout to obtain a decomposed geometry; and

recognizing said circuit element with said decomposed geometry.

19. The method of claim 10, wherein said comparing uses a tolerance.

20. The method of claim 19, wherein said tolerance includes a parameter of said model or a value derived from a parameter of said model.

21. The method of claim 19, wherein said tolerance includes a tolerance region defined by:

decomposing said layout to obtain a decomposed geometry, said decomposed geometry being a point or a shape; and

associating said tolerance region to said decomposed geometry.

22. The method of claim 19, wherein said tolerance includes a tolerance surface, and said determining includes comparing said first description with said tolerance surface.

23. The method of claim 19, wherein said comparing comprises:

computing a difference between said description and said target description; and

comparing said difference with said tolerance.

24. The method of claim 19, wherein said tolerance is determined using an electrical description determined by:

identifying a circuit element with said layout; and

obtaining said electrical description from said circuit element.

25. The method of claim 24, wherein said identifying comprises:

decomposing said layout to obtain a decomposed geometry; and

recognizing said circuit element with said decomposed geometry.

26. The method of claim 10, wherein said description and said target description includes manufacturing and electrical specifications.

27. The method of claim 26, wherein said manufacturing and electrical specifications include one of the following:

modulation transfer function, contrast, exposure latitude, image log slope, normalized image log slope, depth of focus, exposure-defocus window, total window, sensitivity to mask critical dimension error, sensitivity to aberrations, common window, linewidth variability, threshold voltage, leakage current, breakdown electric field, channel-length-modulation parameter, input and output impedance, input and output capacitance, input and output inductance, current density, current gain, unity current gain frequency, or any combination thereof.

28. A method for identifying weak spots in a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a layout of said target patterned layer;

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer;

providing a parameter of said model;

providing a first value and a second value of said parameter of said model;

computing a first description of a portion of said layout using said first value of said parameter, said first parametric representation, and said second parametric representation;

computing a second description of a portion of said layout using said second value of said parameter, said first parametric representation, and said second parametric representation; and

comparing said first description and said second description.

29. The method of claim 28, wherein said comparing uses a design rule defined by the manufacturing and electrical requirements of said integrated circuit.

30. A method for identifying weak spots in a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a layout of said target patterned layer;

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer;

providing a parameter of said model;

providing a first value and a second value of said parameter of said model;

computing a first description of a portion of said layout using said first value of said parameter, said first parametric representation, and said second parametric representation;

performing a first verification based on said first description and said target patterned layer, obtaining a first result;

computing a second description of a portion of said layout using said second value of said parameter, said first parametric representation, and said second parametric representation;

performing a second verification based on said second description and said target patterned layer, obtaining a second result; and

comparing said first result with said second result.

31. The method of claim 30, wherein said comparing uses a design rule defined by the manufacturing and electrical requirements of said integrated circuit.

32. A method for defining a physical connection in a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a layout of said target patterned layer;

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer;

providing a collection of placed cells with abstract interconnectivity information; and

defining said physical connection using said collection with said abstract interconnectivity information, said defining includes computing a description of a portion of said layout using said first parametric representation and said second parametric representation.

33. The method of claim 32, wherein said defining includes checking against a design rule defined by the manufacturing and electrical requirements of said integrated circuit.

35. The method of claim 32, wherein said compacting includes checking against a design rule defined by the manufacturing and electrical requirements of said integrated circuit.

34. A method for compacting a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; and

compacting said layout to obtain a compacted layout, said compacting includes computing a description of a portion of said compacted layout using said first parametric representation and said second parametric representation.

36. A method for layout synthesis of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer;

providing a netlist; and

computing a layout of said netlist, said computing includes computing a description of a portion of said layout using said first parametric representation and said second parametric representation.

37. The method of claim 36, wherein said computing includes checking against a design rule defined by the manufacturing and electrical requirements of said integrated circuit.

38. A method for generating a design rule used in the generation of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a specification of said target patterned layer;

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer;

providing a parameter of said model; and

generating a design rule using said model, said parameter, and said specification, said generating includes computing a description of a layout using said first parametric representation and said second parametric representation.

39. A method for generating a design rule used in the generation of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a template of a design rule;

providing a specification of said template;

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; and

generating a design rule using said model and said specification, said generating includes computing a description of a layout using said first parametric representation and said second parametric representation.

40. A method for extracting an electrical parameter from a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a model that includes at least a first parametric representation characterizing features of the target patterned layer, and a second parametric representation characterizing features of one of the plurality of patterned layers other than the target patterned layer;

computing a description of a portion of said layout using said first parametric representation and said second parametric representation; and

computing said electrical parameter using said description.

41. The method of claim 40, wherein said electrical parameter is one of the following:

parasitic capacitance, parasitic inductance, or parasitic resistance.

42. A method for interactive layout editing of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer;

providing a shape of the layout being drawn;

computing a target description of a portion of said layout including said shape using said target patterned layer of material;

computing a description of a portion of said layout including said shape using said first parametric representation and said second parametric representation;

comparing said description with said target description; and

supplying feedback on said comparing.

43. The method of claim 42, wherein said description is checked against a design rule defined by the manufacturing and electrical requirements of said integrated circuit.

44. The method of claim 42, wherein said feedback includes one of the following:

a suggestion of vertex location, a region of allowable vertex locations, a list of suggestions, a score, a ranking, or any combination thereof.

45. The method of claim 42, wherein said feedback includes an explanation.

46. The method of claim 45, wherein said explanation includes one of the following:

a reason for a suggested location, a reason for a discouraged location, a reason for a disallowed location, or any combination thereof.

47. A method for modifying a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a model that includes at least a first parametric representation characterizing features of the target patterned layer, and a second parametric representation characterizing features of one of the plurality of patterned layers other than the target patterned layer; and

computing a modified layout from a portion of said layout using said model, said computing includes computing a description of a portion of said layout using said first parametric representation and said second parametric representation.

48. The method of claim 47, wherein said model is based on one of the following:

physical theory, approximation, heuristics, or any combination thereof.

49. The method of claim 47, wherein at least one of said parametric representations is one of the following parametric representations:

a lithography process, a mask-making process, an oxidation process, a deposition process, an etching process, an epitaxy process, an ion implantation process, a thermal process, a chemical-mechanical polishing process, a transistor, a capacitor, an inductor, or a resistor.

50. The method of claim 47, wherein said computing a modified layout includes:

optical proximity correction, phase-shifting conversion, mask data preparation, dummy fill insertion, or a combination thereof.

51. The method of claim 47, wherein said description is an electrical description.

52. A method for disposing of an anomaly of a mask fabricated using a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer;

extracting a portion of said layout corresponding to said mask anomaly;

computing a description of said portion of said layout using said first parametric representation and said second parametric representation; and

evaluating whether to repair said mask anomaly based on said description.

53. The method of claim 52, wherein said evaluating includes checking against a design rule defined by the manufacturing and electrical requirements of said integrated circuit.

54. A method for manufacturing an integrated circuit including a plurality of patterned layers of material, said integrated circuit including at least one target patterned layer of material, comprising:

obtaining a computer readable layout of a portion of said target patterned layer of material;

providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer;

performing an operation on said layout to create an output layout using a data processor and using said model, said operation includes computing a description of a portion of said layout using said first parametric representation and said second parametric representation;

producing mask data using said output layout;

producing a mask having a mask layout pattern based on said mask data; and

producing said target patterned layer of material using said mask.

55. The method of claim 54, wherein said operation includes one of the following:

layout editing, layout synthesis, routing, compaction, layout verification, layout modification, or obtaining a layout description.