Design-manufacturing interface via a unified model
First Claim
1. A method for obtaining a layout description for a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
- providing a layout of said target patterned layer;
providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; and
computing a description of a portion of said layout using said first parametric representation and said second parametric representation.
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Accused Products
Abstract
Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have adverse impact on all parts of the integrated circuit creation flow where design rules are used. In addition, segregation of the various layout data modification steps required for deep sub-micrometer manufacturing are resulting in slack and inefficiencies. This invention describes methods to improve integrated circuit creation via the use of a unified model of fabrication processes and circuit elements that can complement or replace design rules. By capturing the interdependence among fabrication processes and circuit elements, the unified model enables efficient layout generation, resulting in better integrated circuits.
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Citations
55 Claims
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1. A method for obtaining a layout description for a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a layout of said target patterned layer; providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; and computing a description of a portion of said layout using said first parametric representation and said second parametric representation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for verifying a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a layout of said target patterned layer; providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one the the plurality of patterned layers other than the target patterned layer; computing a target description of a portion of said layout using said target patterned layer of material; computing a description of a portion of said layout using said first parametric representation and said second parametric representation; and comparing said description with said target description. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A method for identifying weak spots in a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a layout of said target patterned layer; providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; providing a parameter of said model; providing a first value and a second value of said parameter of said model; computing a first description of a portion of said layout using said first value of said parameter, said first parametric representation, and said second parametric representation; computing a second description of a portion of said layout using said second value of said parameter, said first parametric representation, and said second parametric representation; and comparing said first description and said second description. - View Dependent Claims (29)
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30. A method for identifying weak spots in a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a layout of said target patterned layer; providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; providing a parameter of said model; providing a first value and a second value of said parameter of said model; computing a first description of a portion of said layout using said first value of said parameter, said first parametric representation, and said second parametric representation; performing a first verification based on said first description and said target patterned layer, obtaining a first result; computing a second description of a portion of said layout using said second value of said parameter, said first parametric representation, and said second parametric representation; performing a second verification based on said second description and said target patterned layer, obtaining a second result; and comparing said first result with said second result. - View Dependent Claims (31)
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32. A method for defining a physical connection in a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a layout of said target patterned layer; providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; providing a collection of placed cells with abstract interconnectivity information; and defining said physical connection using said collection with said abstract interconnectivity information, said defining includes computing a description of a portion of said layout using said first parametric representation and said second parametric representation. - View Dependent Claims (33, 35)
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34. A method for compacting a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; and compacting said layout to obtain a compacted layout, said compacting includes computing a description of a portion of said compacted layout using said first parametric representation and said second parametric representation.
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36. A method for layout synthesis of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; providing a netlist; and computing a layout of said netlist, said computing includes computing a description of a portion of said layout using said first parametric representation and said second parametric representation. - View Dependent Claims (37)
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38. A method for generating a design rule used in the generation of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a specification of said target patterned layer; providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; providing a parameter of said model; and generating a design rule using said model, said parameter, and said specification, said generating includes computing a description of a layout using said first parametric representation and said second parametric representation.
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39. A method for generating a design rule used in the generation of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a template of a design rule; providing a specification of said template; providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; and generating a design rule using said model and said specification, said generating includes computing a description of a layout using said first parametric representation and said second parametric representation.
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40. A method for extracting an electrical parameter from a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a model that includes at least a first parametric representation characterizing features of the target patterned layer, and a second parametric representation characterizing features of one of the plurality of patterned layers other than the target patterned layer; computing a description of a portion of said layout using said first parametric representation and said second parametric representation; and computing said electrical parameter using said description. - View Dependent Claims (41)
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42. A method for interactive layout editing of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; providing a shape of the layout being drawn; computing a target description of a portion of said layout including said shape using said target patterned layer of material; computing a description of a portion of said layout including said shape using said first parametric representation and said second parametric representation; comparing said description with said target description; and supplying feedback on said comparing. - View Dependent Claims (43, 44, 45, 46)
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47. A method for modifying a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a model that includes at least a first parametric representation characterizing features of the target patterned layer, and a second parametric representation characterizing features of one of the plurality of patterned layers other than the target patterned layer; and computing a modified layout from a portion of said layout using said model, said computing includes computing a description of a portion of said layout using said first parametric representation and said second parametric representation. - View Dependent Claims (48, 49, 50, 51)
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52. A method for disposing of an anomaly of a mask fabricated using a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
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providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; extracting a portion of said layout corresponding to said mask anomaly; computing a description of said portion of said layout using said first parametric representation and said second parametric representation; and evaluating whether to repair said mask anomaly based on said description. - View Dependent Claims (53)
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54. A method for manufacturing an integrated circuit including a plurality of patterned layers of material, said integrated circuit including at least one target patterned layer of material, comprising:
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obtaining a computer readable layout of a portion of said target patterned layer of material; providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; performing an operation on said layout to create an output layout using a data processor and using said model, said operation includes computing a description of a portion of said layout using said first parametric representation and said second parametric representation; producing mask data using said output layout; producing a mask having a mask layout pattern based on said mask data; and producing said target patterned layer of material using said mask. - View Dependent Claims (55)
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Specification