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Design-manufacturing interface via a unified model

  • US 7,155,689 B2
  • Filed: 10/07/2003
  • Issued: 12/26/2006
  • Est. Priority Date: 10/07/2003
  • Status: Expired due to Term
First Claim
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1. A method for obtaining a layout description for a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:

  • providing a layout of said target patterned layer;

    providing a model that includes at least a first parametric representation characterizing at least features of the target patterned layer, and a second parametric representation characterizing at least features of the integrated circuit dependent on one of the plurality of patterned layers other than the target patterned layer; and

    computing a description of a portion of said layout using said first parametric representation and said second parametric representation.

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