Method for co-verifying hardware and software for a semiconductor device

• US 7,155,690 B2
• Filed: 01/30/2004
• Issued: 12/26/2006
• Est. Priority Date: 01/31/2003
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Muraoka, Michiaki, Nishi, Hiroaki, Hirao, Tomoya, Shinsha, Takao, Kowatari, Toshiaki, Fujikake, Hideaki, Ohkuma, Atsushi, Yamashita, Hiroyuki
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US10/766,955
• Publication Number:
  US 20050149897A1
• Time in Patent Office: 1,061 Days
• Field of Search: 716/1, 716/8, 716/18, 716/4, 703/14, 703/17, 703/20, 703/23, 703/27, 714/739, 714/37, 710/113, 717/140, 717/146
• US Class Current: 716/106
• CPC Class Codes: G01R 31/318314 Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages simulation software G01R31/318357; emulators G06F11/261
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.

Claims

1. A method, using a host CPU, for co-verifying hardware and software for a semiconductor device on which at least one target CPU and one OS are mounted, the hardware/software co-verification method comprising the steps of:

(a) inputting, as a verification model, a timed software component described in a C-based language and compiling the same, inputting, as a verification model, a hardware component described in the C-based language and compiling the same, and linking together the compiled timed software component and the compiled hardware component, wherein an interrupt routine scheduler is input that is equivalent to an interrupt processing section of an instruction set simulator but is provided as an independent unit;

(b) inputting a testbench and compiling the same;

(c) linking together the verification models input in step (a) and the teatbench input in step (b);

(d) performing a C-based native code simulation without per-instruction interpretation and execution, based on an executing program generated in step (c); and

(e) outputting a result of the simulation performed in step (d).

2. The hardware/software co-verification method as claimed in claim 1 wherein, in order to generate in advance the timed software component described in the C-based language from an untimed software component described in ANSI-C, the method further comprises the steps of:

inputting the untimed software component described in ANSI-C, and recognizing basic blocks and inserting control points;

generating binary code native to a target CPU by compiling the untimed software component in which the control points have been inserted;

computing execution time between the control points in the generated binary code native to the target CPU; and

inserting, in accordance with the computed execution time, an execution time insertion statement at each of the control points inserted in the untimed software component, and thus outputting the timed software component described in the C-based language.

3. A method, using a host CPU, for co-verifying hardware and software for a semiconductor device on which at least one target CPU and one OS are mounted, the hardware/software co-verification method comprising the steps of:

(a) inputting, as a verification model, a timed software component constructed from binary code native to the host CPU, inputting as a verification model, a hardware component described in a C-based language and compiling the same, and linking together the input timed software component and the compiled hardware component, wherein an interrupt routine scheduler is input that is equivalent to an interrupt processing section of an instruction set simulator but is provided as an independent unit;

(b) inputting a teatbench and compiling the same;

(c) linking together the verification models input in step (a) and the teetbench input in step (b);

(d) performing a C-based native code simulation without per-instruction interpretation and execution, based on an executing program generated in step (c); and

(e) outputting a result of the simulation performed in step (d).

4. The hardware/software co-verification method as claimed in claim 3 wherein, in order to generate in advance the timed software component constructed from the binary code native to the host CPU from an untimed software component constructed from binary code native to a target CPU, the method further comprises the steps of:

inputting the untimed software component constructed from the binary code native to the target CPU, and converting the same into a software component expressed in the binary code native to the host CPU;

recognizing basic blocks and inserting control points in the software component expressed in the binary code native to the host CPU;

computing execution time between the control points in the software component in which the control points have been inserted; and

inserting, in accordance with the computed execution time, binary code functionally equivalent to an execution time insertion statement at each of the control points inserted in the software component, and thus outputting the timed software component constructed from the binary code native to the host CPU.

5. A method, using a host CPU, for co-verifying hardware and software for a semiconductor device on which at least one target CPU and one OS are mounted, the hardware/software co-verification method comprising the steps of:

(a) inputting, as a verification model, a timed software component described in a C-based language and compiling the same, inputting, as a verification model, a timed software component constructed from binary code native to the host CPU and compiling the same, inputting, as a verification model, a hardware component described in the C-based language and compiling the same, and linking together the compiled or input timed software components and the compiled hardware component, wherein an interrupt routine scheduler is input that is equivalent to an interruct processing section of an instruction set simulator but is provided as an independent unit;

(b) inputting a testbench and compiling the same;

(c) linking together the verification models input in step (a) and the testbench input in step (b);

(d) performing a C-based native code simulation without pre-construction interpretation and execution, based on an executing program generated in step (c); and

(e) outputting a result of the simulation performed in step (d).

6. The hardware/software co-verification method as claimed in claim 5 wherein, in order to generate in advance the timed software component described in the C-based language from an untimed software component described in ANSI-C, the method further comprises the steps of:

inputting The untimed software component described in ANSI-C, and recognizing basic blocks and inserting control points;

generating binary code native to a target CPU by compiling the untimed software component in which the control points have been inserted;

computing execution time between the control points in the generated binary code native to the target CPU; and

inserting, in accordance with the computed execution time, an execution time insertion statement at each of the control points inserted in the untimed software component, and thus outputting the timed software component described in the C-based language.

7. The hardware/software co-verification method as claimed in claim 5 wherein, in order to generate in advance the timed software component constructed from the binary code native to the host CPU from an untimed software component constructed from binary code native to a target CPU, the method further comprises the steps of:

inputting the untimed software component constructed from the binary code native to the target CPU, and converting the same into a software component expressed in the binary code native to the host CPU;

recognizing basic blocks end inserting control points in the software component expressed in the binary code native to the host CPU;

computing execution time between the control points in the software component in which the control points have been inserted; and

inserting, in accordance with the computed execution time, binary code functionally equivalent to an execution time insertion statement at each of the control points inserted in the software component, and thus outputting the timed software component constructed from the binary code native to the host CPU.