Thin film transistor array substrate and fabricating method thereof
First Claim
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1. A method of fabricating a thin film transistor array substrate structure, comprising:
- forming a gate line, a gate electrode connected to the gate line, a common line on a substrate, the common line disposed between at least two gate lines, wherein the at least two gate lines and the data line define a pixel area;
forming a gate insulating film on the substrate;
forming a semiconductor layer on the gate insulating film;
forming a data line, a source electrode and a drain electrode on the semiconductor;
forming a protective film on the substrate; and
forming a pixel electrode on the protective film, wherein the gate lines are disposed adjacently to each of at least two pixel areas, and wherein each respective one of odd-numbered gate lines are adjacent to a respective one of pre-stage even-numbered gate lines.
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Abstract
A thin film transistor array substrate structure includes a plurality of data lines; a plurality of gate lines intersecting the data lines to define pixel areas, the gate line being adjacent to at least two pixel areas; a plurality of common lines disposed between the at least two pixel areas; a plurality of thin film transistors formed at each intersection between the gate lines and the data lines; a plurality of common electrodes provided substantially parallel to the common lines; and a plurality of pixel electrodes connected to the thin film transistors.
41 Citations
5 Claims
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1. A method of fabricating a thin film transistor array substrate structure, comprising:
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forming a gate line, a gate electrode connected to the gate line, a common line on a substrate, the common line disposed between at least two gate lines, wherein the at least two gate lines and the data line define a pixel area; forming a gate insulating film on the substrate; forming a semiconductor layer on the gate insulating film; forming a data line, a source electrode and a drain electrode on the semiconductor; forming a protective film on the substrate; and forming a pixel electrode on the protective film, wherein the gate lines are disposed adjacently to each of at least two pixel areas, and wherein each respective one of odd-numbered gate lines are adjacent to a respective one of pre-stage even-numbered gate lines. - View Dependent Claims (2, 3, 4, 5)
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Specification
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Current AssigneeLG Display Co., Ltd.
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Original AssigneeLG Philips LCD Company Limited (LG Display Co., Ltd.)
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InventorsSon, Hyeon-Ho
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Primary Examiner(s)Lee; Calvin
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Application NumberUS11/003,370Publication NumberTime in Patent Office757 DaysField of Search349/39, 349/43, 349/48, 349/141, 257/59, 257/296, 257/88, 438/29, 438/69, 438/74, 438/116, 438/129, 438/149US Class Current438/74CPC Class CodesG02F 1/134363 for applying an electric fi...H01L 27/124 with a particular compositi...
