Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

• US 7,157,378 B2
• Filed: 07/06/2004
• Issued: 01/02/2007
• Est. Priority Date: 07/06/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Barns, Chris E., Doczy, Mark L., Kavalieros, Jack, Brask, Justin K., Metz, Matthew V., Datta, Suman, Miller, Anne E.
• Primary Examiner(s): Fourson; George R.
• Assistant Examiner(s): Maldonado; Julio J.
• Application Number:
  US10/885,958
• Publication Number:
  US 20060008968A1
• Time in Patent Office: 910 Days
• Field of Search: 438/183, 438/216, 438/287, 438/591, 438/653, 438/654, 438/656, 438/722, 438/626, 438/627, 438/628, 438/240, 438/244, 438/254, 438/387, 438/397, 438/704, 438/FOR.193, 257/E21.444, 257/E21.453, 257/E21.624, 257/E21.625, 257/E21.638, 257/E21.639, 257/E21.655
• US Class Current: 438/704
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

Claims

1. A method for making a semiconductor device comprising:

forming a dielectric layer on a substrate;

forming a trench within the dielectric layer;

forming a high-k gate dielectric layer within the trench;

forming a first metal layer on the high-k gate dielectric layer;

forming a second metal layer on the first metal layer;

removing at least part of the second metal layer from above the dielectric layer using a chemical mechanical polishing step; and

removing at least part of the first metal layer and the high-k gate dielectric layer from above the dielectric layer using a plasma dry etch step.

2. The method of claim 1 wherein the high-k gate dielectric layer comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

3. The method of claim 1 wherein the first metal layer comprises a workfunction metal that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.

4. The method of claim 3 wherein the first metal layer is between about 25 and about 300 angstroms thick, and has a workfunction that is between about 3.9 eV and about 4.2 eV.

5. The method of claim 3 wherein the first metal layer is between about 25 and about 300 angstroms thick, and has a workfunction that is between about 4.9 eV and about 5.2 eV.

6. The method of claim 1 wherein the second metal layer comprises a fill metal that is selected from the group consisting of titanium nitride, tungsten, titanium, aluminum, tantalum, tantalum nitride, cobalt, copper, and nickel.

7. The method of claim 1 wherein substantially all of the second metal layer is removed from above the dielectric layer using the chemical mechanical polishing step.

8. The method of claim 7 wherein substantially all of the first metal layer that remains after the chemical mechanical polishing step is removed from above the dielectric layer using the plasma dry etch step.

9. The method of claim 7 wherein substantially all of the high-k gate dielectric layer that remains after the chemical mechanical polishing step is removed from above the dielectric layer using the plasma dry etch step.

10. A method for making a semiconductor device comprising:

forming a dielectric layer on a substrate;

forming a trench within the dielectric layer;

forming a high-k gate dielectric layer within the trench;

forming a first metal layer on the high-k gate dielectric layer;

forming a sealant layer on the first metal layer;

forming a second metal layer on the metal carbide sealant layer;

removing the second metal layer and at least part of the sealant layer from above the dielectric layer using a chemical mechanical polishing step; and

removing at least part of the first metal layer and the high-k gate dielectric layer from above the dielectric layer using a plasma dry etch step.

11. The method of claim 10 wherein the high-k gate dielectric layer comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

12. The method of claim 10 wherein the first metal layer comprises a workfunction metal that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.

13. The method of claim 12 wherein the first metal layer is between about 25 and about 300 angstroms thick, and has a workfunction that is between about 3.9 eV and about 4.2 eV.

14. The method of claim 12 wherein the first metal layer is between about 25 and about 300 angstroms thick, and has a workfunction that is between about 4.9 eV and about 5.2 eV.

15. The method of claim 10 wherein the second metal layer comprises a fill metal that is selected from the group consisting of titanium nitride, tungsten, titanium, aluminum, tantalum, tantalum nitride, cobalt, copper, and nickel.

16. The method of claim 10 wherein the sealant layer comprises a material that is selected from the group consisting of a metal carbide, a metal carbide alloy, a metal nitride, and a metal nitride alloy.

17. The method of claim 16 wherein the sealant layer is formed using an atomic layer chemical vapor deposition process and comprises a material that is selected from the group consisting of titanium carbide, titanium nitride, and tantalum nitride.

18. A method for making a semiconductor device comprising:

forming a dielectric layer on a substrate;

forming a trench within the dielectric layer;

forming a high-k gate dielectric layer within the trench;

forming a first metal layer on the high-k gate dielectric layer;

forming a sealant layer on the first metal layer;

forming a second metal layer on the sealant layer;

removing at least part of the second metal layer from above the dielectric layer using a chemical mechanical polishing step; and

removing at least part of the sealant, the first metal layer, and the high-k gate dielectric layer from above the dielectric layer using a plasma dry etch step.

19. The method of claim 18 wherein:

the high-k gate dielectric layer comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate;

the first metal layer comprises a workfunction metal that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide;

the sealant layer comprises a material that is selected from the group consisting of a metal carbide, a metal carbide alloy, a metal nitride, and a metal nitride alloy; and

the second metal layer comprises a fill metal that is selected from the group consisting of titanium nitride, tungsten, titanium, aluminum, tantalum, tantalum nitride, cobalt, copper, and nickel.

20. The method of claim 18 wherein:

substantially all of the second metal layer is removed from above the dielectric layer using a chemical mechanical polishing step; and

substantially all of the first metal layer that remains after the chemical mechanical polishing step and substantially all of the high-k gate dielectric layer are removed from above the dielectric layer using a dry etch step.