Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices

• US 7,157,787 B2
• Filed: 05/26/2004
• Issued: 01/02/2007
• Est. Priority Date: 02/20/2002
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kim, Sarah E., List, R. Scott, Kellar, Scot A.
• Primary Examiner(s): Graybill; David E.
• Application Number:
  US10/855,032
• Publication Number:
  US 20040219763A1
• Time in Patent Office: 951 Days
• Field of Search: None
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

Claims

1. A wafer system, comprising:

a first wafer, the first wafer having a front side and a back side;

a first tapered via formed in the first wafer through an active layer of the back side of the first wafer and an interlayer dielectric layer of the front side of the first wafer, the first tapered via having a larger face and a smaller face, the larger face located at the back side of the first wafer;

a second wafer, the second wafer having a front side and a back side, the back side of the second wafer facing the back side of the first wafer; and

a second tapered via formed in the second wafer, the second tapered via having a larger face and a smaller face, the larger face located at the back side of the second wafer and bonded to the larger face of the first tapered via.

2. The wafer system of claim 1, further comprising:

a plurality of tapered vias formed in the first wafer and a corresponding plurality of tapered vias formed in the second wafer, the plurality of tapered vias in the first wafer having larger faces bonded to the larger faces of the corresponding plurality of tapered vias in the second wafer.

3. The wafer system of claim 1, wherein the tapered vias include a conductive metal.

4. The wafer system of claim 1, further comprising:

a first plurality of metallic lines formed at the front side of the first wafer; and

a third wafer, the third wafer having a front side and a back side and having a second plurality of metallic lines formed at the front side of the third wafer;

wherein the front side of the third wafer faces the front side of the first wafer and wherein the first plurality of metallic lines is bonded to the second plurality of metallic lines.

5. The wafer system of claim 4, wherein the first plurality of metallic lines is bonded to the second plurality of metallic lines by metal diffusion bonding.

6. The wafer system of claim 4, further comprising at least one conductive via formed in the third wafer, the at least one conductive via coupled to one or more tapered vias in the first wafer.

7. The wafer system of claim 6, further comprising at least one pad or C4 bump formed at the back side of the third wafer and coupled to the at least one conductive via.

8. The wafer system of claim 4, further comprising:

a third plurality of metallic lines formed at the front side of the second wafer; and

a fourth wafer, the fourth wafer having a front side and a back side and having a fourth plurality of metallic lines formed at the front side of the fourth wafer;

wherein the front side of the fourth wafer faces the front side of the second wafer and wherein the third plurality of metallic lines is bonded to the fourth plurality of metallic lines.

9. The wafer system of claim 8, wherein the third plurality of metallic lines is bonded to the fourth plurality of metallic lines by metal diffusion bonding.

10. A microelectronic package, comprising:

a first die, the first die having a front side and a back side;

a first tapered via formed in the first die through an active layer of the back side of the first wafer and an interlayer dielectric layer of the front side of the first wafer, the first tapered via having a larger face and a smaller face, the larger face located at the back side of the first die;

a second die, the second die having a front side and a back side, the back side of the second die facing the back side of the first die; and

a second tapered via formed in the second die, the second tapered via having a larger face and a smaller face, the larger face located at the back side of the second die and bonded to the larger face of the first tapered via.

11. The microelectronic package of claim 10, further comprising:

a plurality of tapered vias formed in the first die and a corresponding plurality of tapered vias formed in the second die, the plurality of tapered vias in the first die having larger faces bonded to the larger faces of the corresponding plurality of tapered vias in the second die.

12. The microelectronic package of claim 10, wherein the tapered vias include a conductive metal.

13. The microelectronic package of claim 10, further comprising:

a first plurality of metallic lines formed at the front side of the first die; and

a third die, the third die having a front side and a back side and having a second plurality of metallic lines formed at the front side of the third die;

wherein the front side of the third die faces the front side of the first die and wherein the first plurality of metallic lines is bonded to the second plurality of metallic lines.

14. The microelectronic package of claim 13, wherein the first plurality of metallic lines is bonded to the second plurality of metallic lines by metal diffusion bonding.

15. The microelectronic package of claim 13, further comprising at least one conductive via formed in the third die, the at least one conductive via coupled to one or more tapered vias in the first die.

16. The microelectronic package of claim 15, further comprising at least one pad or solder bump formed at the back side of the third die and coupled to the at least one conductive via.

17. The microelectronic package of claim 13, further comprising:

a third plurality of metallic lines formed at the front side of the second die; and

a fourth die, the fourth die having a front side and a back side and having a fourth plurality of metallic lines formed at the front side of the fourth die;

wherein the front side of the fourth die faces the front side of the second die and wherein the third plurality of metallic lines is bonded to the fourth plurality of metallic lines.

18. The microelectronic package of claim 17, wherein the third plurality of metallic lines is bonded to the fourth plurality of metallic lines by metal diffusion bonding.

19. The microelectronic package claim 16, further comprising at least one external interconnect coupled to the at least one pad or solder bump.

20. A vertically stacked multiple wafer system, comprising:

a first bonded wafer pair including a first wafer, a second wafer, and a first set of metallic lines formed in interlayer dielectrics on opposing surfaces of the first wafer and the second wafer, the first set of metallic lines bonding the first wafer to the second wafer and electrically connecting active devices of the first and second wafers;

a second bonded wafer pair including a third wafer, a fourth wafer, and a second set of metallic lines formed in interlayer dielectrics on opposing surfaces of the third wafer and the fourth wafer, the second set of metallic lines bonding the third wafer to the fourth wafer and electrically connecting active devices of the third and fourth wafers;

a first tapered via formed in the second wafer through an active layer of a back side of the second wafer and an interlayer dielectric layer of a front side of the second wafer, the first tapered via having a first end connected to a metallic line in the first set of metallic lines and a second end at the back side of the second wafer, the first end having a smaller area than the second end; and

a second tapered via formed in the third wafer, the second tapered via having a third end at a back side of the third wafer and a fourth end connected to a metallic line in the second set of metallic lines, the third end having a larger area than the fourth end, wherein the third end of the second tapered via is bonded to the second end of the first tapered via to bond the first bonded wafer pair to the second bonded wafer pair.

21. The wafer system of claim 20, wherein the first tapered via and the second tapered via each comprises a conductive metal formed within insulated sidewalls.

22. The wafer system of claim 20, wherein each of the second wafer and the third wafer is thinner than the first wafer.

23. A vertically stacked wafer system comprising:

a first wafer comprising;

a first front side having an interlayer dielectric layer;

a first back side having an active layer; and

a first via comprising a first section formed in the interlayer dielectric layer and a second section formed in the active layer, the second section having a horizontal cross-sectional area larger than a horizontal cross-sectional area of the first section; and

a second wafer comprising;

a second front side;

a second back side facing the first back side of the first wafer; and

a second via comprising a third section formed in the second back side and a fourth section formed in the second front side, wherein a surface of the third section is bonded to a surface of the second section bonding the first wafer to the second wafer.

24. The wafer system of claim 23, wherein the first via further comprises a barrier layer deposited on a bottom surface of the second section.

25. The wafer system of claim 23, wherein the first wafer supports one of:

a microprocessor, a memory device, or a communication device; and

the second wafer supports a different one of;

the microprocessor, the memory device, or the communication device.

26. A vertically stacked wafer system comprising:

a first bonded wafer pair including a first wafer, a second wafer, and a first set of metallic lines formed in interlayer dielectrics on opposing surfaces of the first wafer and the second wafer, the first set of metallic lines bonding the first wafer to the second wafer and electrically connecting active devices of the first and second wafers;

a second bonded wafer pair including a third wafer, a fourth wafer, and a second set of metallic lines formed in interlayer dielectrics on opposing surfaces of the third wafer and the fourth wafer, the second set of metallic lines bonding the third wafer to the fourth wafer and electrically connecting active devices of the third and fourth wafers;

a first pair of bonded interwafer vias including;

a first interwafer via formed in the second wafer, the first interwafer via having a first surface located at a back side of the second wafer, the first interwafer via extending through an active layer of the back side of the second wafer and an interlayer dielectric layer of a front side of the second wafer; and

a second interwafer via formed in the third wafer, the second interwafer via having a second surface located at a back side of the third wafer, the second interwafer via extending through an active layer of the back side of the third wafer and an interlayer dielectric layer of a front side of the third wafer, the second surface of the second interwafer via bonded to the first surface of the first interwafer via; and

a pair of bonded dummy vias including;

a first dummy via having a third surface located at the back side of the second wafer, the first dummy via ending in the active layer of the back side of the second wafer; and

a second dummy via having a fourth surface located at the back side of the third wafer, the second dummy via ending in the active layer of the back side of the third wafer, the fourth surface of the second dummy via bonded to the third surface of the first dummy via.

27. The wafer system of claim 26, wherein the first dummy via has a diameter smaller than a diameter of the first interwafer via.

28. The wafer system of claim 26, wherein the first interwafer via is tapered.

29. The wafer system of claim 26, wherein the pair of bonded dummy vias is a heat conduit for an active IC device in the wafer system.