Robust ramp controlled enable for voltage regulator

• US 7,157,892 B1
• Filed: 11/28/2005
• Issued: 01/02/2007
• Est. Priority Date: 11/28/2005
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Micrel Incorporated (Microchip Technology Incorporated)
• Inventors: Ritter, David Wayne
• Primary Examiner(s): Vu; Bao Q.
• Application Number:
  US11/288,882
• Time in Patent Office: 400 Days
• Field of Search: 323/282, 323/284, 323/901, 323/906, 323/288, 363/49
• US Class Current: 323/284
• CPC Class Codes: G05F 1/468 characterised by reference voltage circuitry, e.g. soft start, remote shutdown
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: Y10S 323/901 Starting circuits

Abstract

A voltage regulator including a bandgap control circuit that maintains the regulator'"'"'s bandgap voltage at a predetermined voltage level after an externally generated enable signal is de-asserted until the regulated output voltage has dropped below a predetermined low reference voltage. The bandgap control circuit includes a latch that is set by the enable control signal to generate a bandgap control signal, which is used to activate a bandgap reference generator that generates the bandgap voltage. The latch is reset to de-assert the bandgap control signal by a logic gate and a low output voltage detector. The detector generates a low output voltage detection signal when the regulated output voltage falls below a low reference voltage. The logic gate generates a rising edge signal that resets the latch only when the enable signal is de-asserted and the detector generates the detection signal, thereby preventing unintended shutdown of the bandgap reference generator.

Claims

1. A voltage regulator for generating a regulated output voltage in response to an externally supplied enable control signal, the voltage regulator comprising:

a bandgap reference generator for generating a bandgap voltage having a predetermined voltage level;

a soft-start control circuit for generating a ramped voltage that gradually increases during a startup period and gradually decreases during a shutdown period, the startup period occurring after the enable control signal is asserted, and the shutdown period occurring after the enable control signal is de-asserted;

a reference voltage comparator having a first input terminal connected to the soft-start control circuit and a second input terminal connected to the bandgap reference generator, wherein the reference voltage comparator includes including means for generating a reference signal that is equal to the ramped voltage while the ramped voltage is lower than the predetermined voltage level of the bandgap signal, and is equal to the bandgap signal when the predetermined voltage level is lower than the ramped voltage;

an output circuit for generating the regulated output voltage in response to the reference signal; and

a bandgap control circuit for controlling the bandgap reference generator to maintain the bandgap voltage at the predetermined voltage level during the shutdown period until the regulated output voltage decreases below a predetermined low reference voltage.

2. The voltage regulator according to claim 1, wherein the bandgap control circuit comprises means for controlling the bandgap reference generator to generate the bandgap voltage immediately after the enable control signal is asserted.

3. The voltage regulator according to claim 2, wherein said means for controlling the bandgap reference generator comprises a latch having a set terminal coupled to receive the enable control signal.

4. The voltage regulator according to claim 3, wherein the bandgap control circuit further comprises:

a low output voltage detector for generating a low output voltage detection signal when the regulated output voltage falls below a low reference voltage; and

a logic gate for generating a reset signal when the enable control signal is de-asserted and the low output voltage detection signal is asserted.

5. The voltage regulator according to claim 4, wherein the logic gate comprises a logic AND gate.

6. The voltage regulator according to claim 1, further comprising a timing control circuit for controlling the soft-start control circuit to gradually increase the ramped voltage during the startup period, and to gradually decrease the ramped voltage during the shutdown period.

7. The voltage regulator according to claim 6, wherein the timing control circuit further comprises means for asserting a power on reset control signal only when the externally supplied enable control signal is asserted and the regulated output voltage is within a predetermined percentage of a predetermined target voltage level.

8. The voltage regulator according to claim 7, further comprising means for comparing a portion of the regulated output voltage with the reference signal, for transmitting an output voltage monitor signal to the timing control circuit when the regulated output voltage is within the predetermined percentage of the predetermined target voltage level.

9. The voltage regulator according to claim 1, wherein the output circuit comprises:

a voltage divider for generating a feedback voltage that is equal to the regulated output voltage multiplied by a predetermined divider ratio;

an error amplifier having a first input terminal connected to the reference voltage comparator and a second input terminal connected to receive the feedback signal; and

an output driver circuit for generating generates the regulated output voltage in response to an output signal generated by the error amplifier.

10. A voltage regulator for generating a regulated output voltage in response to an externally supplied enable control signal, the voltage regulator comprising:

means for generating a bandgap voltage having a predetermined voltage level;

means for generating a ramped voltage that gradually increases during a startup period and gradually decreases during a shutdown period, the startup period occurring after the enable control signal is asserted, and the shutdown period occurring after the enable control signal is de-asserted;

means for generating a reference signal that is equal to the ramped voltage while the ramped voltage is lower than the predetermined voltage level of the bandgap signal, and is equal to the bandgap signal when the predetermined voltage level is lower than the ramped voltage;

means for generating the regulated output voltage in response to the reference signal; and

means for controlling the bandgap reference generator to maintain the bandgap voltage at the predetermined voltage level during the shutdown period until the regulated output voltage decreases below a predetermined low reference voltage.

11. A method for controlling a voltage regulator to generate a regulated output voltage in response to an externally supplied enable control signal, the method comprising:

generating a bandgap voltage having a predetermined voltage level;

generating a ramped voltage that gradually increases during a startup period and gradually decreases during a shutdown period, the startup period occurring after the enable control signal is asserted, and the shutdown period occurring after the enable control signal is de-asserted;

generating a reference signal that is equal to the ramped voltage while the ramped voltage is lower than the predetermined voltage level of the bandgap signal, and is equal to the bandgap signal when the predetermined voltage level is lower than the ramped voltage;

generating the regulated output voltage in response to the reference signal; and

controlling the bandgap reference generator to maintain the bandgap voltage at the predetermined voltage level during the shutdown period until the regulated output voltage decreases below a predetermined low reference voltage.