Rail-to-rail-input buffer

• US 7,157,970 B2
• Filed: 08/27/2004
• Issued: 01/02/2007
• Est. Priority Date: 08/27/2003
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Dawes, Alan
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): Flanagan; Krista M.
• Application Number:
  US10/927,947
• Publication Number:
  US 20050083124A1
• Time in Patent Office: 858 Days
• Field of Search: None
• US Class Current: 330/253
• CPC Class Codes: H03F 3/45112 Complementary long tailed pairs having parallel inputs and being supplied in parallel

Abstract

A rail-to-rail-Input Buffer with constant mutual conductance includes a differential input; a first differential stage supplied with a first reference current; a second differential stage supplied with a second reference current; a switching PMOS-transistor which switches through when the input signal is higher than a first threshold voltage to divert the first reference current to a first current mirror circuit; a switching NMOS-transistor which switches through when an input signal is lower than a second threshold voltage to divert the second reference current to a second current mirror circuit; a third differential stage supplied with the mirrored first reference current and replaces the first differential stage when the input signal is higher than the first threshold voltage; and a fourth differential stage supplied with the mirrored second reference current and replaces the second differential stage when the input signal is lower than the second threshold voltage.

Claims

1. A buffer circuit comprising:

a differential input configured to receive an input signal;

a first differential stage supplied with a first reference current, the first differential stage comprising PMOS-transistors having gate terminals connected to the differential input;

a second differential stage supplied with a second reference current, the second differential stage comprising NMOS-transistors having gate terminals connected to the differential input;

a switching PMOS-transistor operable to, when the input signal is higher than a predetermined first threshold voltage, divert the first reference current from the first differential stage to a first current mirror circuit configured to mirror the first reference current;

a switching NMOS-transistor operable to, when the input signal is lower than a predetermined second threshold voltage, divert the second reference current from the second differential stage to a second current mirror circuit configured to mirror the second reference current;

a third differential stage comprising NMOS-transistors having gate terminals connected to the differential input, wherein the third differential stage is configured to receive the mirrored first reference current when the input signal is higher than the first threshold voltage;

a fourth differential stage comprising PMOS-transistors having gate terminals connected to the differential input, wherein the fourth differential stage is configured to receive the mirrored second reference current when the input signal is lower than the second threshold voltage;

a third current mirror circuit operably connected to receive a first output current of the third differential stage, and operable to mirror the first output current of the third differential stage to a first output current line; and

a fourth current mirror circuit operably connected to receive a second output current of the third differential stage, and operable to mirror the second output current of the third differential stage to a second output current line; and

wherein the third differential state comprises two NMOS-transistors having drain terminals connected to the first current mirror circuit.

2. The buffer circuit according to claim 1 wherein the switching PMOS-transistor includes a gate terminal operably coupled to receive a reference voltage.

3. The buffer circuit according to claim 1 wherein the switching NMOS-Transistor includes a gate terminal operably coupled to receive a reference voltage.

4. The buffer circuit according to claim 1 wherein the first differential stage comprises two PMOS-transistors having drain terminals operably connected to a source of the first reference current and having source terminals operably connected to first and second output current lines.

5. The buffer circuit according to claim 4 wherein the second differential stage comprises two NMOS-transistors having drain terminals connected to a source of the second reference current and having source terminals operably connected to third and fourth output current lines.

6. The buffer circuit according to claim 5 wherein the first, second, third and fourth output current lines are connected to a current summing circuit, the current summing circuit operable to sum currents on the first, second, third and fourth output current lines to generate an output sum current.

7. The buffer circuit according to claim 6 wherein the current summing circuit is operably connected to provide the output sum current to an output stage driver.

8. The buffer circuit according to claim 1 wherein the first current mirror circuit comprises two NMOS-transistors having interconnected gate terminals.

9. The buffer circuit according to claim 1 wherein the second current mirror circuit comprises two PMOS-transistors having interconnected gate terminals.

10. The buffer circuit according to claim 1 further comprising:

a fifth current mirror circuit operably connected to receive a first output current of the fourth differential stage, and operable to mirror the first output current of the fourth differential stage to a third output current line; and

a sixth current mirror circuit operably connected to receive a second output current of the fourth differential stage, and operable to mirror the second output current of the fourth differential stage to a fourth output current line; and

wherein the fourth differential stage comprises two PMOS-transistors having drain terminals connected to the second current mirror circuit.

11. The buffer circuit according to claim 1 further comprising:

a third current mirror circuit operably connected to receive a first output current of the fourth differential stage, and operable to mirror the first output current of the fourth differential stage to a third output current line; and

a fourth current mirror circuit operably connected to receive a second output current of the fourth differential stage, and operable to mirror the second output current of the fourth differential stage to a fourth output current line; and

wherein the fourth differential stage comprises two PMOS-transistors having drain terminals connected to the second current mirror circuit.

12. The buffer circuit according to claim 1, further comprising:

a current summing circuit configured to generated a summed output current; and

an output stage driver operably coupled to amplify the summed output current, the output stage driver including an output operably coupled to an input terminal of the differential input.

13. A buffer circuit having first, second and third operating states, the buffer circuit comprising:

a differential input configured to receive an input signal;

a first differential stage supplied with a first reference current, the first differential stage comprising PMOS-transistors having gate terminals connected to the differential input, the first differential stage configured to generate output currents when the buffer circuit is in the first operating state and when the buffer circuit is in the second operating state;

a second differential stage supplied with a second reference current, the second differential stage comprising NMOS-transistors having gate terminals connected to the differential input, the second differential stage configured to generate output currents when the buffer circuit is in the second operating state and when the buffer circuit is in the third operating state;

a third differential stage comprising NMOS-transistors having gate terminals connected to the differential input, wherein the third differential stage is configured to generate output currents when the buffer circuit is in the third operating state;

a fourth differential stage comprising PMOS-transistors having gate terminals connected to the differential input, wherein the fourth differential stage is configured to generate output currents when the buffer circuit is in the first operating state;

a third current mirror circuit operably connected to receive a first output current of the third differential stage, and operable to mirror the first output current of the third differential state to a first output current line; and

a fourth current mirror circuit operably connected to receive a second output current of the third differential stage, and operable to mirror the second output current of the third differential stage to a second output current line; and

wherein the third differential stage comprises two NMOS-transistors having drain terminals connected to the first current mirror circuit.

14. The buffer circuit of claim 13, wherein the first, second, third and fourth differential stages are operably coupled to a current summing circuit.

15. The buffer circuit of claim 13, further comprising a first switch operably coupled to divert the first reference current away from the first differential stage when the buffer circuit is in the third operating state.

16. The buffer circuit of claim 15, further comprising a second switch operably coupled to divert the second reference current away from the second differential stage when the buffer circuit is in the first operating state.

17. The buffer circuit of claim 15, wherein the first switch comprises a PMOS-transistor.

18. The buffer circuit of claim 15 further comprising a first current mirror coupled between the first switch and the third differential stage.

19. The buffer circuit of claim 15 further comprising a first current mirror coupled between a first output of the third differential stage and a buffer circuit output, and a second current mirror coupled between a second output of the third differential stage and the buffer circuit output.