MEMS-based, computer systems, clock generation and oscillator circuits and LC-tank apparatus for use therein
First Claim
1. A clock generation circuit, the circuit comprising:
- a substrate;
a double-balanced, cross-coupled voltage-controlled, reference oscillator fabricated on the substrate and including a micro-electromechanical LC-tank apparatus for generating a differential sinusoidal periodic signal, the LC-tank apparatus comprising a parallel plate capacitor and an inductor fabricated in a plurality of CMOS metal interconnect layers, the parallel plate capacitor comprising a top plate suspended in air over the substrate and moveable in response to a control voltage, and the inductor supported in air over the substrate;
first circuitry also fabricated on the substrate for converting the differential sinusoidal periodic signal into a single-ended, high frequency, square-wave digital output signal; and
a cascoded current source coupled through at least one transistor to the reference oscillator.
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Abstract
MEMS-based, computer system, clock generation and oscillator circuits and LC-tank apparatus for use therein are provided and which are fabricated using a CMOS-compatible process. A micromachined inductor (L) and a pair of varactors (C) are developed in metal layers on a silicon substrate to realize the high quality factor LC-tank apparatus. This micromachined LC-tank apparatus is incorporated with CMOS transistor circuitry in order to realize a digital, tunable, low phase jitter, and low power clock, or time base, for synchronous integrated circuits. The synthesized clock signal can be divided down with digital circuitry from several GHz to tens of MHZ—a systemic approach that substantially improves stability as compared to the state of the art. Advanced circuit design techniques have been utilized to minimize power consumption and mitigate transistor flicker noise upconversion, thus enhancing clock stability.
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Citations
68 Claims
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1. A clock generation circuit, the circuit comprising:
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a substrate; a double-balanced, cross-coupled voltage-controlled, reference oscillator fabricated on the substrate and including a micro-electromechanical LC-tank apparatus for generating a differential sinusoidal periodic signal, the LC-tank apparatus comprising a parallel plate capacitor and an inductor fabricated in a plurality of CMOS metal interconnect layers, the parallel plate capacitor comprising a top plate suspended in air over the substrate and moveable in response to a control voltage, and the inductor supported in air over the substrate; first circuitry also fabricated on the substrate for converting the differential sinusoidal periodic signal into a single-ended, high frequency, square-wave digital output signal; and a cascoded current source coupled through at least one transistor to the reference oscillator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An oscillator circuit comprising:
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a substrate; a double-balanced, cross-coupled micro-electromechanical LC-tank apparatus fabricated on the substrate with a CMOS-compatible process; first circuitry fabricated on the substrate with the CMOS-compatible process and coupled to the LC-tank apparatus to generate a sinusoidal periodic signal having an original frequency; second circuitry fabricated on the substrate with the CMOS-compatible process and coupled to the first circuitry to convert the sinusoidal periodic signal to a plurality of square-wave periodic signals having a corresponding plurality of application frequencies, each application frequency of the plurality of application frequencies equal to the original frequency divided by an integer; and a cascoded current source coupled through at least one transistor to the LC-tank apparatus. - View Dependent Claims (10, 11, 12, 13)
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14. A micromachined LC-tank apparatus, the apparatus comprising:
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a substrate; at least one micromachined, parallel plate varactor fabricated on the substrate with a CMOS-compatible process in conductive layers; a micromachined inductor coupled to the at least one varactor and also fabricated on the substrate with the CMOS-compatible process in a conductive layer of the conductive layers; a cascoded current source coupled through at least one transistor to the inductor or to the varactor; wherein the varactor has a first predetermined size and the inductor has a second predetermined size to generate a sinusoidal signal having an original frequency during oscillation; and circuitry coupled to the varactor and the inductor to divide the original frequency to a lower application frequency. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A computer system comprising:
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a databus; a central processing unit coupled to the databus; a memory coupled to the databus; and a clock generation circuit for generating a square-wave digital output signal, the clock generation circuit comprising; a double-balanced, cross-coupled reference harmonic oscillator comprising an inductor and a capacitor for generating a reference sinusoidal periodic signal having a first frequency; a cascoded current source coupled through at least one transistor to the reference harmonic oscillator; and first circuitry fabricated on the substrate for converting the sinusoidal periodic signal into a square-wave digital output signal having a second frequency, the second frequency equal to or lower than the first frequency.
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29. A clock generation circuit, the circuit comprising:
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a balanced, cross-coupled reference harmonic oscillator for generating a reference sinusoidal signal having an original frequency, the reference harmonic oscillator comprising an inductor coupled to a capacitor; a cascoded current source coupled to the reference harmonic oscillator; first circuitry coupled to the reference harmonic oscillator to convert the reference sinusoidal signal into a square-wave digital output signal having a first frequency, the first frequency lower than the original frequency; and second circuitry fabricated on the substrate for dividing the first frequency of the square-wave digital output signal to at least one application frequency, the at least one application frequency lower than the first frequency. - View Dependent Claims (30, 31, 32)
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33. An oscillator oscillator circuit for generating a periodic signal, the oscillator circuit comprising:
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a substrate; a double-balanced, cross-coupled LC-tank apparatus fabricated on the substrate with a CMOS-compatible process, the LC-tank comprising at least one micromachined varactor having a capacitance which varies in response to the control input and having a top plate; a cascoded current source coupled to the LC-tank apparatus; circuitry fabricated on the substrate with the CMOS-compatible process and coupled to the LC-tank apparatus to generate the periodic signal and including a bypass capacitor to block the control input to the top plate from the remainder of the circuitry.
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34. An LC-tank apparatus, the apparatus comprising:
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a substrate; at least one voltage-controlled micromachined varactor fabricated on the substrate with a CMOS-compatible process, the at least one micromachined varactor having a variable capacitance to provide a tuning range for the apparatus, the at least one micromachined varactor comprising a fixed bottom plate and a movable top plate suspended above the bottom plate; a micromachined inductor coupled to the at least one varactor and fabricated on the substrate with the CMOS-compatible process; and a cascoded current source coupled to the micromachined varactor or the micromachined inductor.
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35. An integrated clock generation circuit, comprising:
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a reference harmonic oscillator circuit to generate a first, reference differential periodic signal having a first frequency, the reference harmonic oscillator circuit comprising an inductor coupled to a capacitor; a cascoded current source coupled through at least one transistor to the reference harmonic oscillator circuit; a frequency divider circuit coupled to the oscillator circuit to convert the first, reference differential periodic signal to a plurality of single-ended square-wave periodic application signals, each periodic application signal having a different frequency equal to a fraction of the first frequency. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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50. An integrated clock generation circuit, comprising:
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a reference oscillator circuit to generate a first, reference differential periodic signal having a first frequency, the oscillator circuit comprising an inductor coupled to a capacitor; an amplifier coupled to the reference oscillator circuit to convert the first, reference differential periodic signal to a single-ended signal having a second frequency; and a frequency divider circuit coupled to the amplifier to convert the single-ended signal to a plurality of square-wave periodic application signals, each periodic application signal having a different frequency equal to or less than the second frequency. - View Dependent Claims (51, 52, 53, 54, 55, 56, 57, 58)
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59. An integrated clock generation circuit, comprising:
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a double-balanced harmonic oscillator circuit, the harmonic oscillator circuit for generating a reference differential periodic signal having a first frequency, the harmonic oscillator circuit comprising an inductor and a capacitor; an amplifier coupled to the reference oscillator circuit to convert the reference differential periodic signal to a single-ended signal having a second frequency; and a frequency divider circuit coupled to the amplifier to convert the single-ended signal to a plurality of square-wave periodic application signals, each periodic application signal having a different frequency equal to a division of the second frequency, wherein a periodic application signal of the plurality of square-wave periodic application signals is a clock signal.
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60. A clock generation circuit, comprising:
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a voltage controlled, reference harmonic oscillator circuit for generating a differential, reference sinusoidal signal having a first frequency, the reference harmonic oscillator comprising an inductor and a first capacitor; a second, common-mode capacitor coupled to the reference harmonic oscillator circuit; a cascoded current source coupled to the reference harmonic oscillator circuit; and first circuitry coupled to the reference harmonic oscillator circuit to convert the differential, reference sinusoidal signal to a single-ended square-wave periodic signal having a second frequency, the second frequency equal to a fraction of the first frequency. - View Dependent Claims (61, 62, 63, 64, 65, 66)
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67. An integrated clock generation circuit, comprising:
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a voltage-controlled, double-balanced reference harmonic oscillator circuit to generate a differential reference periodic signal having a first frequency, the reference harmonic oscillator circuit comprising an inductor coupled to a varactor; a cascoded current source coupled to the reference harmonic oscillator circuit; first circuitry coupled to the reference harmonic oscillator circuit to convert the differential reference periodic signal to a single-ended signal having a second frequency; and a frequency divider circuit coupled to the first circuitry to convert the single-ended signal to a plurality of square-wave periodic application signals, each periodic application signal having a different frequency equal to or less than the second frequency, wherein a clock signal is an application signal of the plurality of square-wave periodic application signals. - View Dependent Claims (68)
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Specification