Analog to digital converter using sawtooth voltage signals with differential comparator

• US 7,158,067 B2
• Filed: 01/31/2005
• Issued: 01/02/2007
• Est. Priority Date: 01/31/2005
• Status: Expired due to Fees

• Current Assignee: United States Department Of Health And Human Services (Government of the United States of America)
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Perkins, F. Keith, Peckerar, Martin, Lauritzen, Keir C., Hodge-Miller, Angela M.
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US11/053,756
• Publication Number:
  US 20060170580A1
• Time in Patent Office: 701 Days
• Field of Search: 341/118, 341/120, 341/144, 341/155, 341/156, 341/158, 341/159, 341/170, 341/136, 341/166, 327/108, 327/132, 327/184, 327/540, 327/131, 332/109, 713/500
• US Class Current: 341/155
• CPC Class Codes: H03M 1/368 having a single comparator per bit, e.g. of the folding type

Abstract

An analog to digital converter includes a resistor-divider network including a plurality of resistors, an arbel channel circuit configured to generate a voltage sawtooth signal as an output, a dc-offset disposed to couple a node of the resistor-divider network and the arbel-channel circuit. The converter further includes a voltage reference circuit configured to generate a reference voltage, and a differential comparator configured to compare the voltage sawtooth signal with the reference voltage to produce a digital output signal corresponding to the voltage sawtooth signal. Method of converting an analog signal to a digital signal is also described.

Claims

1. An N-bit analog-to-digital converter comprising:

at least one branch, each branch having;

a resistor-divider network including a plurality of resistors;

a first circuit configured to generate a voltage sawtooth signal as an output;

a DC offset circuit disposed to couple a node of the resistor-divider network and the first circuit;

a voltage reference circuit configured to generate a reference voltage; and

a differential comparator configured to compare the voltage sawtooth signal with the reference voltage to produce a digital output signal corresponding to the voltage sawtooth signal,

the first circuit including 2^N-n cells for each bit of the first circuit, wherein n is the current bit.

2. The analog-to-digital converter of claim 1, wherein the cells are coupled to a load resistor, the load resistor being tied to the differential comparator.

3. The analog-to-digital converter of claim 2, wherein each of the cells comprise at least first, second, and third sections, the first section being configured to generate a voltage drop, the second section being configured as a buffer section, and the third section being configured to generate a voltage sawtooth signal.

4. The analog-to-digital converter of claim 3, wherein the third section is designed using an all CMOS process.

5. The analog-to-digital converter of claim 2, wherein the differential comparator is designed for a single rail power supply.

6. The analog-to-digital converter of claim 1, wherein the differential comparator comprises a non-inverting input configured to receive the sawtooth signal, and an inverting input coupled to the voltage reference circuit.

7. The analog-to-digital converter of claim 1, wherein N-bit conversion of an analog signal to a digital signal is performed using N differential comparators.

8. The analog-to-digital converter of claim 1, wherein multiple cycles of voltage sawtooth signals are generated from a single ramp.

9. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises a self-encoding design using reduced number of differential comparators.

10. The analog-to-digital converter of claim 1, wherein a total number of branches equals N, and the number of cells in each branch'"'"'s first circuit equals 2^N-n.

11. An apparatus for converting an analog signal to a digital signal, comprising:

a resistor-divider network;

a first circuit configured to generate a voltage sawtooth signal as an output, the first circuit including 2^N-n cells for each bit of the first circuit, wherein N is the total number of bits and n is the current bit;

a DC offset circuit disposed to couple a node of the resistor-divider network and the first circuit;

a voltage reference circuit configured to generate a reference voltage; and

a differential comparator configured to compare the voltage sawtooth signal with the reference voltage to produce a digital output signal corresponding to the voltage sawtooth signal.

12. The apparatus of claim 11, wherein each of the cells includes a first section configured to generate a voltage drop, a second section configured as a buffer section, and a third section configured to generate the voltage sawtooth signal.

13. The apparatus of claim 12, wherein the third section comprises at least first, second, and third transistors, the first transistor being configured as a pull-up transistor, the second transistor being configured as a pull-down transistor.

14. The apparatus of claim 13, wherein a source contact of the pull-up transistor is connected to a drain contact of the pull-down transistor as well as a drain contact of the third transistor, the third transistor being configured to isolate the functionality of the cell.

15. The apparatus of claim 12, wherein the third section is designed using an all CMOS process.

16. The apparatus of claim 12, wherein the second section comprises at least a resistor and transistors configured as a common drain amplifier, wherein at least of the transistors is configured as a depletion mode shunt transistor.

17. The apparatus of claim 11, wherein the cells are coupled to a load resistor, the load resistor being tied to the differential comparator.

18. The apparatus of claim 17, wherein the differential comparator is designed for a single rail power supply.

19. The apparatus of claim 11, wherein the differential comparator comprises a non-inverting input configured to receive the voltage sawtooth signal, and the inverting input is coupled to the voltage reference circuit.

20. The apparatus of claim 11, wherein N-bit conversion of an analog signal to a digital signal is performed using N differential comparators.

21. The apparatus of claim 11, wherein multiple cycles of voltage sawtooth signals are generated from a single ramp.

22. A method of converting an analog signal to a digital signal, comprising:

generating a voltage sawtooth signal using a first circuit, the first circuit having a plurality of cells, each cell being coupled to a load resistor, the load resistor being tied to a differential comparator, each cell having at least first, second, and third sections, the first section being configured to generate a voltage drop, the second section being configured as a buffer section, and the third section being configured to generate a voltage sawtooth signal and having at least one pull-up transistor and one pull-down transistor;

generating a reference voltage; and

comparing the voltage sawtooth signal with the reference voltage to produce a digital output signal corresponding to the voltage sawtooth signal.

23. The method of claim 22, wherein the comparing is performed using a differential comparator.

24. The method of claim 22, wherein N-bit conversion of an analog signal to a digital signal is performed using N differential comparators.

25. The method of claim 22, wherein the circuit includes 2^N-n cells for each bit of the first circuit, wherein N is the total number of bits and n is the current bit.

26. An N-bit analog-to-digital converter, comprising:

N branches, each branch configured to receive an input voltage and output a voltage sawtooth; and

a voltage divider section connecting inputs of the N branches,

each branch including at least one cell,

each cell having a circuit configured to generate a voltage sawtooth based on the input voltage, the circuit having at least a first, a second, and a third transistor, the first transistor being configured as a pull-up transistor, and the second transistor being configured as a pull-down transistor.

27. The analog-to-digital converter of claim 26, wherein a source contact of the pull-up transistor is connected to a drain contact of the pull-down transistor and to a drain contact of the third transistor.

28. The analog-to-digital converter of claim 27, the third transistor being configured to isolate the functionality of the cell.

29. The analog-to-digital converter of claim 27, wherein each branch has a number of cells equal to 2^N-n, wherein n is a number of a current bit.