Three-dimensional memory system-on-a-chip

• US 7,158,220 B2
• Filed: 10/19/2004
• Issued: 01/02/2007
• Est. Priority Date: 10/19/2004
• Status: Expired due to Fees

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Pert, Evan
• Application Number:
  US10/967,893
• Publication Number:
  US 20060081883A1
• Time in Patent Office: 805 Days
• Field of Search: 365/51, 365/63, 257/211
• US Class Current: 356/51
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/30 having the source region and the drain region on the same level, e.g. lateral transistors

Abstract

The present invention provides a three-dimensional memory (3D-M) system-on-a-chip (SoC). It takes full advantage of the difference in the number of interconnect levels between the embedded processor (eP) and embedded memory (eM) in an SoC chip. The un-used interconnect space on top of the eM block is converted into 3D-M. This conversion incurs minimum additional cost, but with significant benefits: 3D-M can add a large storage capacity to the SoC chip and therefore the chip becomes more powerful.

Claims

1. A system-on-a-chip integrated circuit, comprising:

an embedded processor (eP) block and an embedded memory (eM) block;

a three-dimensional memory (3D-M) block stacked on top of at least a portion of said eM block, said 3D-M block comprising at least one 3D-M level, said 3D-M level comprising a plurality of address-selection lines and 3D-M cells.

2. The system-on-a-chip integrated circuit according to claim 1, wherein said 3D-M is an electrically-programmable 3D-M (EP-3DM).

3. The system-on-a-chip integrated circuit according to claim 1, wherein said 3D-M is a non-electrically-programmable 3D-M (NEP-3DM).

4. The system-on-a-chip integrated circuit according to claim 1, wherein:

at least a portion of said eM block uses fewer interconnect levels than said eP block;

said 3D-M block is located on top of at least said portion of said eM block.

5. The system-on-a-chip integrated circuit according to claim 1, wherein:

said eP block further comprises a first conductor and a second conductor;

said 3D-M block further comprises a word line and a bit line; and

said word line and said first conductor are at the same first interconnect level, said bit line and said second conductor are at the same second interconnect level.

6. The system-on-a-chip integrated circuit according to claim 1, further comprising at least one full 3D-M level covering at least a portion of said eP block.

7. The system-on-a-chip integrated circuit according to claim 1, wherein said 3D-M block comprises a plurality of 3D-M pillars, upper address-selection lines and lower address-selection lines, said 3D-M pillars being located between selected ones of said upper address-selection lines and said lower address-selection lines.

8. The system-on-a-chip integrated circuit according to claim 7, further comprising a half-via providing electrical conduction between selected ones of said upper address-selection lines and said 3D-M pillars.

9. The system-on-a-chip integrated circuit according to claim 7, wherein

one dimension of said 3D-M pillar is equal to the width of said upper address-selection line;

and

the other dimension of said 3D-M pillar is equal to the width of said lower address-selection line.

10. The system-on-a-chip integrated circuit according to claim 1, wherein said 3D-M block comprises a plurality of 3D-M junctions, upper address-selection lines and lower address-selection lines, said 3D-M junctions being naturally formed at the intersection of selected ones of said upper address-selection lines and said lower address-selection lines.