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Asymmetric static random access memory device having reduced bit line leakage

  • US 7,158,402 B2
  • Filed: 08/06/2003
  • Issued: 01/02/2007
  • Est. Priority Date: 08/06/2003
  • Status: Active Grant
First Claim
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1. An SRAM device, comprising:

  • a column of asymmetric memory cells spanning opposing bit lines in alternating orientations; and

    a sense amplifier including;

    sensing circuitry configured to sense stored values in said cells; and

    switching circuitry configured to adapt the sensing circuitry as a function of said orientations.

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