Delay-lock loop and method adapting itself to operate over a wide frequency range

• US 7,158,443 B2
• Filed: 06/01/2005
• Issued: 01/02/2007
• Est. Priority Date: 06/01/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lin, Feng
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): Tran; Anthan
• Application Number:
  US11/142,946
• Publication Number:
  US 20060274597A1
• Time in Patent Office: 580 Days
• Field of Search: 365/233, 365/194, 327/156, 327/158
• US Class Current: 365/189.07
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate a plurality of output signals. During an initialization period, an initialization circuit sets the delay of the delay line to a minimum delay value and then compares this delay value to the period of the input clock signal. Based on this comparison, the initialization circuit programs the programmable divider and adjusts the number of delayed clock signals combined to generate the output signals. More specifically, as the frequency of the reference clock signal increases, the divider is programmed to divide by a greater number, and a larger number of delay clock signals are combined to generate the output signals.

Claims

1. A system for providing at least one periodic output clock signal, comprising:

a programmable frequency divider having an input terminal receiving an input clock signal, a control terminal receiving a divider select signal, and an output terminal, the programmable frequency being operable to divide the frequency of the input clock signal by an integer number determined by the select signal to generate a clock signal at the output terminal;

a delay-lock loop having phase detector and a delay line, the delay line of the delay-lock loop having an input terminal coupled to the output terminal of the programmable frequency divider so that the clock signal generated by the programmable frequency divider propagates through the delay line to generate the at least one periodic output clock signal; and

an initialization circuit coupled to the programmable frequency divider and the delay-lock loop, the initialization circuit being operative during an initialization period to set the delay of the delay line to a minimum delay value and to compare the timing of the at least one periodic output clock signal to the timing of the input clock signal, the initialization circuit generating the select signal with a value determined by the timing comparison.

2. The system of claim 1 further comprising a phase mixer coupled to the delay line to receive a plurality of signals having a plurality of different phases, the phase mixer being operable to combine the signals received from the delay line to generate a plurality of periodic output clock signals.

3. The system of claim 2 wherein the phase mixer is coupled to receive the select signal from the initialization circuit, the phase mixer being operable to combine the signals received from the delay line based on the value of the select signal.

4. The system of claim 2 wherein the phase mixer is operable to generate the plurality of output clock signals at a frequency that is equal to the frequency of the input clock signal if the select signal programs the programmable frequency divider to divide the frequency of the input clock signal by one.

5. The system of claim 2 wherein the phase mixer is operable to generate the plurality of output clock signals at a frequency that is half the frequency of the input clock signal if the select signal programs the programmable frequency divider to divide the frequency of the input clock signal by two.

6. The system of claim 2 wherein the phase mixer is operable to generate the plurality of output clock signals at a frequency that is half the frequency of the input clock signal if the select signal programs the programmable frequency divider to divide the frequency of the input clock signal by four.

7. The system of claim 2 wherein the phase mixer comprises a multiplexer having a plurality of sets of input terminals coupled to receive different combinations of signals from the delay line of the delay-lock loop, the multiplexer further comprising a control input coupled to receive the select signal, the multiplexer being operable to couple one of the sets of input terminals to a set of output terminals based on the value of the select signal.

8. The system of claim 7 wherein a first one of the sets of input terminals of the multiplexer is coupled to receive four signals from the delay line of the delay-lock loop having different phases, and wherein the phase mixer further comprises:

a frequency divider that receives two signals having different phases from the delay line of the delay-lock loop, the frequency divider generating four signals from the two received signals that are coupled to a second one of the sets of input terminals of the multiplexer;

a clock generating circuit that receives eight signals having different phases from the delay line of the delay-lock loop, the clock generating circuit generating four signals from the eight received signals that are coupled to a third one of the sets of input terminals of the multiplexer.

9. The system of claim 8 wherein the multiplexer is operable to couple the first set of input terminals to the set of output terminals responsive to the select signal when the select signal causes the frequency divider to divide the frequency of the input clock signal by two, to couple the second set of input terminals to the set of output terminals responsive to the select signal when the select signal causes the frequency divider to divide the frequency of the input clock signal by one, and to couple the third set of input terminals to the set of output terminals responsive to the select signal when the select signal causes the frequency divider to divide the frequency of the input clock signal by four.

10. The system of claim 8 wherein the clock generating circuit comprises a pair of exclusive OR gate each of which receives signals from the delay line of the delay-lock loop having alternating phases.

11. The system of claim 1 wherein the phase detector of the delay-lock loop has a first input terminal coupled to receive the clock signal at the output terminal of the programmable frequency divider and a second input terminal coupled to receive the at least one periodic output clock signal from the delay line.

12. The system of claim 1 wherein the phase detector of the delay-lock loop has a first input terminal coupled to receive the input signal applied to the input terminal of the programmable frequency divider and a second input terminal coupled to receive the at least one periodic output clock signal from the delay line.

13. A memory device, comprising:

a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;

a column address circuit operable to receive and decode column address signals applied to the external address terminals;

a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;

a read data path circuit operable to couple read data signals from the memory cell array to external data terminals of the memory device, the read data signals being applied to the external data terminals responsive to a read data strobe signal;

a write data path circuit operable to couple write data signals from the external data terminals of the memory device responsive to a write data strobe signal, the write data signals being coupled to the memory cell array;

a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;

a strobe generating circuit operable to generate either the write data strobe signal or the read data strobe signal from an internal clock signal, the strobe generating circuit comprising;

a programmable frequency divider having an input terminal receiving a reference clock signal, a control terminal receiving a divider select signal, and an output terminal, the programmable frequency divider being operable to divide the frequency of the reference clock signal by an integer number determined by the select signal to generate a clock signal at the output terminal;

a delay-lock loop having phase detector and a delay line, the delay line of the delay-lock loop having an input terminal coupled to the output terminal of the programmable frequency divider so that the clock signal generated by the programmable frequency divider propagates through the delay line to generate the at least one periodic output clock signal from which either the write data strobe signal or the read data strobe signal is derived; and

an initialization circuit coupled to the programmable frequency divider and the delay-lock loop, the initialization circuit being operative during an initialization period to set the delay of the delay line to a minimum delay value and to compare the timing of the at least one periodic output clock signal to the timing of the reference clock signal, the initialization circuit generating the select signal with a value determined by the timing comparison.

14. The memory device of claim 13 further comprising a phase mixer coupled to the delay line to receive a plurality of signals having a plurality of different phases, the phase mixer being operable to combine the signals received from the delay line to generate a plurality of periodic output clock signals.

15. The memory device of claim 14 wherein the phase mixer is coupled to receive the select signal from the initialization circuit, the phase mixer being operable to combine the signals received from the delay line based on the value of the select signal.

16. The memory device of claim 14 wherein the phase mixer is operable to generate the plurality of output clock signals at a frequency that is equal to the frequency of the reference clock signal if the select signal programs the programmable frequency divider to divide the frequency of the reference clock signal by one.

17. The memory device of claim 14 wherein the phase mixer is operable to generate the plurality of output clock signals at a frequency that is half the frequency of the reference clock signal if the select signal programs the programmable frequency divider to divide the frequency of the reference clock signal by two.

18. The memory device of claim 14 wherein the phase mixer is operable to generate the plurality of output clock signals at a frequency that is half the frequency of the reference clock signal if the select signal programs the programmable frequency divider to divide the frequency of the reference clock signal by four.

19. The memory device of claim 14 wherein the phase mixer comprises a multiplexer having a plurality of sets of input terminals coupled to receive different combinations of signals from the delay line of the delay-lock loop, the multiplexer further comprising a control input coupled to receive the select signal, the multiplexer being operable to couple one of the sets of input terminals to a set of output terminals based on the value of the select signal.

20. The memory device of claim 19 wherein a first one of the sets of input terminals of the multiplexer is coupled to receive four signals from the delay line of the delay-lock loop having different phases, and wherein the phase mixer further comprises:

a frequency divider that receives two signals having different phases from the delay line of the delay-lock loop, the frequency divider generating four signals from the two received signals that are coupled to a second one of the sets of input terminals of the multiplexer;

a clock generating circuit that receives eight signals having different phases from the delay line of the delay-lock loop, the clock generating circuit generating four signals from the eight received signals that are coupled to a third one of the sets of input terminals of the multiplexer.

21. The memory device of claim 20 wherein the multiplexer is operable to couple the first set of input terminals to the set of output terminals responsive to the select signal when the select signal causes the frequency divider to divide the frequency of the reference clock signal by two, to couple the second set of input terminals to the set of output terminals responsive to the select signal when the select signal causes the frequency divider to divide the frequency of the reference clock signal by one, and to couple the third set of input terminals to the set of output terminals responsive to the select signal when the select signal causes the frequency divider to divide the frequency of the reference clock signal by four.

22. The memory device of claim 20 wherein the clock generating circuit comprises a pair of exclusive OR gate each of which receives signals from the delay line of the delay-lock loop having alternating phases.

23. The memory device of claim 13 wherein the phase detector of the delay-lock loop has a first input terminal coupled to receive the clock signal at the output terminal of the programmable frequency divider and a second input terminal coupled to receive the at least one periodic output clock signal from the delay line.

24. The memory device of claim 13 wherein the phase detector of the delay-lock loop has a first input terminal coupled to receive the input signal applied to the input terminal of the programmable frequency divider and a second input terminal coupled to receive the at least one periodic output clock signal from the delay line.

25. The memory device of claim 13 wherein the memory device comprises a dynamic random access memory device.

26. A processor-based system, comprising

a processor having a processor bus;

an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a memory device coupled to the processor bus adapted to allow data to be stored, the memory device comprising;

a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;

a column address circuit operable to receive and decode column address signals applied to the external address terminals;

a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;

a read data path circuit operable to couple read data signals from the memory cell array to external data terminals of the memory device, the read data signals being applied to the external data terminals responsive to a read data strobe signal;

a write data path circuit operable to couple write data signals from the external data terminals of the memory device responsive to a write data strobe signal, the write data signals being coupled to the memory cell array;

a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;

a strobe generating circuit operable to generate either the write data strobe signal or the read data strobe signal from an internal clock signal, the strobe generating circuit comprising;

a programmable frequency divider having an input terminal receiving a reference clock signal, a control terminal receiving a select signal, and an output terminal, the programmable frequency divider being operable to divide the frequency of the reference clock signal by an integer number determined by the select signal to generate a clock signal at the output terminal;

a delay-lock loop having phase detector and a delay line, the delay line of the delay-lock loop having an input terminal coupled to the output terminal of the programmable frequency divider so that the clock signal generated by the programmable frequency divider propagates through the delay line to generate the at least one periodic output clock signal from which either the write data strobe signal or the read data strobe signal is derived; and

an initialization circuit coupled to the programmable frequency divider and the delay-lock loop, the initialization circuit being operative during an initialization period to set the delay of the delay line to a minimum delay value and to compare the timing of the at least one periodic output clock signal to the timing of the reference clock signal, the initialization circuit generating the select signal with a value determined by the timing comparison.

27. The processor-based system of claim 26 further comprising a phase mixer coupled to the delay line to receive a plurality of signals having a plurality of different phases, the phase mixer being operable to combine the signals received from the delay line to generate a plurality of periodic output clock signals.

28. The processor-based system of claim 27 wherein the phase mixer is coupled to receive the select signal from the initialization circuit, the phase mixer being operable to combine the signals received from the delay line based on the value of the select signal.

29. The processor-based system of claim 27 wherein the phase mixer is operable to generate the plurality of output clock signals at a frequency that is equal to the frequency of the reference clock signal if the select signal programs the programmable frequency divider to divide the frequency of the reference clock signal by one.

30. The processor-based system of claim 27 wherein the phase mixer is operable to generate the plurality of output clock signals at a frequency that is half the frequency of the reference clock signal if the select signal programs the programmable frequency divider to divide the frequency of the reference clock signal by two.

31. The processor-based system of claim 27 wherein the phase mixer is operable to generate the plurality of output clock signals at a frequency that is half the frequency of the reference clock signal if the select signal programs the programmable frequency divider to divide the frequency of the reference clock signal by four.

32. The processor-based system of claim 27 wherein the phase mixer comprises a multiplexer having a plurality of sets of input terminals coupled to receive different combinations of signals from the delay line of the delay-lock loop, the multiplexer further comprising a control input coupled to receive the select signal, the multiplexer being operable to couple one of the sets of input terminals to a set of output terminals based on the value of the select signal.

33. The processor-based system of claim 32 wherein a first one of the sets of input terminals of the multiplexer is coupled to receive four signals from the delay line of the delay-lock loop having different phases, and wherein the phase mixer further comprises:

a frequency divider that receives two signals having different phases from the delay line of the delay-lock loop, the frequency divider generating four signals from the two received signals that are coupled to a second one of the sets of input terminals of the multiplexer;

a clock generating circuit that receives eight signals having different phases from the delay line of the delay-lock loop, the clock generating circuit generating four signals from the eight received signals that are coupled to a third one of the sets of input terminals of the multiplexer.

34. The processor-based system of claim 33 wherein the multiplexer is operable to couple the first set of input terminals to the set of output terminals responsive to the select signal when the select signal causes the frequency divider to divide the frequency of the reference clock signal by two, to couple the second set of input terminals to the set of output terminals responsive to the select signal when the select signal causes the frequency divider to divide the frequency of the reference clock signal by one, and to couple the third set of input terminals to the set of output terminals responsive to the select signal when the select signal causes the frequency divider to divide the frequency of the reference clock signal by four.

35. The processor-based system of claim 33 wherein the clock generating circuit comprises a pair of exclusive OR gate each of which receives signals from the delay line of the delay-lock loop having alternating phases.

36. The processor-based system of claim 26 wherein the phase detector of the delay-lock loop has a first input terminal coupled to receive the clock signal at the output terminal of the programmable frequency divider and a second input terminal coupled to receive the at least one periodic output clock signal from the delay line.

37. The processor-based system of claim 26 wherein the phase detector of the delay-lock loop has a first input terminal coupled to receive the input signal applied to the input terminal of the programmable frequency divider and a second input terminal coupled to receive the at least one periodic output clock signal from the delay line.

38. The processor-based system of claim 26 wherein the memory device comprises a dynamic random access memory device.