Mailbox registers for synchronizing header processing execution

• US 7,158,520 B1
• Filed: 03/22/2002
• Issued: 01/02/2007
• Est. Priority Date: 03/22/2002
• Status: Expired due to Fees

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Libby, Jeffrey G., Sindhu, Pradeep, Lim, Raymond M.
• Primary Examiner(s): Pham; Chi
• Assistant Examiner(s): JAIN, RAJ K
• Application Number:
  US10/102,961
• Time in Patent Office: 1,747 Days
• Field of Search: 370/392, 370/352, 370/353, 370/401, 370/389, 709/236, 709/230
• US Class Current: 370/392
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3072 Packet splitting
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 69/325 in the network layer [OSI layer 3], e.g. X.25 H04L69/16 takes precedence

Abstract

A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. Mailbox registers allow the L2 and L3 header generation units to communicate with one another. The L2 header generation unit may write to a specified mailbox register only when a valid bit corresponding to the mailbox register indicates that the register does not contain valid data. After writing to the mailbox register, the L2 header generation unit changes the state of the valid bit. The L3 register then reads from the mailbox register and changes the state of the valid bit. A similar implementation of the mailbox registers allows data to flow from the L3 header generation unit to the L2 header generation unit.

Claims

1. A packet header processing engine comprising:

a first packet processing unit configured to generate first packet header information relating to a packet header;

a second packet processing unit implemented in parallel with the first packet processing unit and configured to generate second packet header information relating to the packet header; and

a first mailbox register through which the first packet processing and the second packet processing unit communicate.

2. The packet header processing engine of claim 1, further comprising:

a second mailbox register through which the second packet processing unit transmits information to the first packet processing unit.

3. The packet header processing engine of claim 1, further comprising:

a second mailbox register through which the first packet processing unit transmits information to the second packet processing unit.

4. The packet header processing engine of claim 1, wherein the first mailbox register includes:

a valid bit indicating whether the first mailbox register is available to be written by the first processing unit.

5. The packet header processing engine of claim 4, wherein the first packet processing unit, after writing to the first mailbox register, sets the valid bit to indicate that the first mailbox register contains valid information.

6. The packet header processing engine of claim 5, wherein the second packet processing unit reads from the first mailbox register when the valid bit indicates that the first mailbox register contains valid information and wherein the second processing units waits until the first packet processing unit changes the state of the corresponding valid bit before reading from the first mailbox register when the valid bit does not indicate that the mailbox register contains valid information.

7. The packet header processing engine of claim 6, wherein the second packet processing unit, after reading from the first mailbox register, sets the corresponding valid bit to indicate that the first mailbox register no longer contains valid information.

8. The packet header processing engine of claim 2, wherein the second mailbox register includes:

a valid bit indicating whether the second mailbox register is available to be written by the second processing unit.

9. The packet header processing engine of claim 8, wherein the second packet processing unit, after writing to the second mailbox register, sets the valid bit to indicate that the second mailbox register contains valid information.

10. The packet header processing engine of claim 1, further comprising:

a host processor; and

a second mailbox register configured to allow the first and second processing units to communicate with the host processor.

11. The packet header processing engine of claim 1, wherein the first packet header information is related to a layer 2 (L2) packet protocol.

12. The packet header processing engine of claim 11, further comprising:

an instruction memory operatively coupled to the first packet processing unit, the instruction memory providing the first packet processing unit with instructions relating to processing of the L2 packet protocol.

13. The packet header processing engine of claim 1, wherein the second packet header information is related to a layer 3 (L3) packet protocol.

14. The packet header processing engine of claim 13, further comprising:

an instruction memory operatively coupled to the second packet processing unit, the instruction memory providing the second packet processing unit with instructions relating to processing of the L3 packet protocol.

15. A method comprising:

receiving packet header information for a packet;

generating, via a first packet processing engine, first protocol information for the packet based on the received packet header information;

generating, via a second packet processing engine, second protocol information for the packet based on the received packet header information;

transmitting information from the first packet processing unit to the second packet processing unit through a first mailbox register; and

transmitting information from the second packet processing unit to the first packet processing unit through a second mailbox register.

16. The method of claim 15, wherein the first mailbox register is configured to only be written to by the first packet processing engine and read from by the second packet processing engine.

17. The method of claim 15, wherein the first packet processing engine writes to the first mailbox register only when a valid bit indicates that the first mailbox register does not contain valid information.

18. The method of claim 17, wherein the first packet processing engine sets the valid bit to indicate that the particular one of the registers contains valid information after writing to the particular one of the registers.

19. The method of claim 15, wherein the second packet processing engine reads from the first mailbox register only when a valid bit indicates that the first mailbox register contains valid information.

20. The method of claim 19, wherein the second packet processing engine sets the valid bit to indicate that the first mailbox register does not contain valid information after reading from the first mailbox register.

21. The method of claim 16, wherein the second mailbox register is configured to only be written to by the second packet processing engine and read from by the first packet processing engine.

22. A network device for processing packets comprising:

a buffer configured to store the packets, including header data and payload data for the packets;

a descriptor reader component coupled to the buffer, the descriptor reader component receiving the header data for the packets stored in the buffer and looking up descriptor information relating to the received packet header data; and

a packet header processing component coupled to the descriptor reader component, the packet header processing component receiving the packet header data and the descriptor information from the descriptor reader component, the packet header processing component including

an input memory configured to store incoming packet header data and descriptor information of a packet,

a first packet processing unit configured to generate, based on the packet header data and the descriptor information of the packet stored in the input memory, first packet header data relating to a first packet header protocol,

a second packet processing unit configured to generate, based on the packet header data and the descriptor information of the packet stored in the input memory, second packet header data relating to a second packet header protocol,

a first mailbox register through which the first packet processing unit transmits information to the second packet processing unit, and

a second mailbox register through which the second packet processing unit transmits information to the first packet processing unit.

23. The network device of claim 22, wherein the descriptor reader component looks up the descriptor information in memory.

24. The network device of claim 22, wherein the network device is a network router.

25. The network device of claim 22, wherein the first mailbox register includes:

a valid bit indicating whether the first mailbox register is available to be written by the first packet processing unit.

26. The network device of claim 25, wherein the first packet processing unit, after writing to the first mailbox register, sets the valid bit to indicate that the first mailbox register contains valid information.

27. The network device of claim 22, wherein the second packet processing unit reads from the first mailbox register when a valid bit indicates that the first mailbox register contains valid information and wherein, when the valid bit does not indicate that the first mailbox register contains valid information, the second processing units waits until the first packet processing unit changes the state of the corresponding valid bit before reading from the first mailbox register.

28. The network device of claim 27, wherein the second packet processing unit, after reading from the first mailbox register, sets the valid bit to indicate that the first mailbox register no longer contains valid information.