Method and device for identifying a data packet in a data stream

• US 7,158,598 B2
• Filed: 10/19/2001
• Issued: 01/02/2007
• Est. Priority Date: 10/19/2000
• Status: Active Grant

• Current Assignee: Crystal Mountain Communications, LLC (Ascend Innovation Management, LLC)
• Original Assignee: Nokia Corporation
• Inventors: Schetelig, Markus, Kafemann, Harald
• Primary Examiner(s): Kim; Kevin
• Application Number:
  US09/981,903
• Publication Number:
  US 20020048330A1
• Time in Patent Office: 1,901 Days
• Field of Search: 375/368, 375/355, 375/365, 375/317, 370/514
• US Class Current: 375/368
• CPC Class Codes: H04L 25/062 Setting decision thresholds using feedforward techniques only
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04W 24/00 Supervisory, monitoring or testing arrangements

Abstract

The invention relates to a method and a device for identifying a data packet in a data stream, in which by means of a d.c. voltage quota determining circuit (30) the d.c. voltage quota (dc) for a demodulated digital input signal (S_in) is calculated, in which a k-bit word is allocated to the input signal (S_in), in that for each symbol of the input signal (S_in) corresponding to a bit a bit value (1 or 0) is determined by a decoding circuit (37) as a function of the d.c. voltage quota (dc), in which the k-bit word corresponding to the input signal (S_in) is compared by a comparison and correlation calculating circuit (41) with an expected k-bit synchronization word in order to determine a correlation value (c_v) and in which a packet identification signal (Pd) is generated by a correlation value comparison circuit (43) if the correlation value (c_v) is greater than a correlation threshold value (c_th). Calculation of the d.c. voltage quota (dc) is therein repeated continually at least until a packet identification signal (Pd) indicates that a data packet is being received.

Claims

1. A method for identifying a data packet in a data stream in which

a d.c. voltage quota for a demodulated digital input signal is calculated in that the input signal is scanned in order to generate a sequence of scanned values and from a selected number of the sequence of scanned values the d.c. voltage quota of the input signal is calculated;

a k-bit word is allocated to the input signal for that for each symbol of the input signal corresponding to a bit, a bit value is determined as a function of the d.c. voltage quota;

the k-bit word corresponding to the input signal is compared with an expected k-bit synchronization word in order to determine a correlation value; and

a packet identification signal is generated if the correlation value is greater than a correlation threshold value; and

wherein

the d.c. voltage quota of the input signal is calculated again after each scan of the input signal at least until the correlation value determined by comparison of the k-bit word corresponding to the input signal with an expected k-bit synchronization word is greater than the correlation threshold value.

2. The method according to claim 1, wherein after a packet identification signal has been generated, the corresponding correlation value is stored and scanning of the input signal calculation of the d.c. voltage quota, and comparison of the k-bit word with an expected k-bit synchronization word to determine the correlation value are still continued for a predetermined period of time and a new packet identification signal is generated if a newly determined correlation value is greater than the correlation threshold value and greater than the previously determined stored correlation value.

3. The method according to claim 2, wherein to determine the k-bit word corresponding to the input signal, the input signal is scanned in order to generate a sequence of scanned values and a bit value is allocated to each scanned value of a selected multiplicity of scanned values as a function of the d.c. voltage quota of the input signal.

4. The method according to claim 3, wherein the input signal is scanned at a frequency which is chosen in such a way that an over-scanning rate is at least equal to two, that therefore at least two scanned values are determined for each symbol and to form the k-bit word corresponding to the input signal in each case only one scanned value per symbol is selected.

5. The method according to claim 2, wherein the multiplicity of scanned values for forming the k-bit word corresponding to the input signal is selected from the sequence of scanned values in such a way that the selected scanned values within the sequence in each case are substantially the same distance apart.

6. The method according to claim 5, wherein the number of scanned values for calculating the d.c. voltage quota of the input signal is chosen in such a way that the scanned values correspond to areas in the expected k-bit synchronization word which substantially have the same number of bits with the value 0 and bits with the value 1 and the d.c. voltage quota is calculated as an average value of the scanned values.

7. The method according to claim 6, wherein the number of scanned values for calculating the d.c. voltage quota consists of at least one group of scanned values in direct succession to one another, which correspond to successive symbols.

8. The method according to claim 6, wherein the number of scanned values for calculating the d.c. voltage quota consists of two groups of scanned values, which are separated from one another by scanned values.

14. The method according claim 1, wherein after a packet identification signal has been generated, the corresponding correlation value is stored and scanning of the input signal, calculation of the d.c. voltage quotas and comparison of the k-bit word corresponding to the input signal with an expected k-bit synchronization word to determine the correlation value are still continued for a predeterminable period of time and a new packet identification signal is generated if a newly determined correlation value is greater than the correlation threshold value and greater than the previously determined stored correlation value.

15. The method according to claim 7, wherein the number of scanned values for calculating the d.c. voltage quota consists of two groups of scanned values, which are separated from one another by a multiplicity of scanned values.

19. The method according to claim 6, wherein the number of scanned values for calculating the d.c. voltage quota includes at least one group of scanned values in direct succession to one another, which correspond to successive symbols.

21. The method according to claim 6, wherein the number of scanned values for calculating the d.c. voltage quota includes two groups of scanned values, which are separated from one another by scanned values.

9. A device for identifying data packets in a data receiving stream with a delay line which has a number of storage places, in which scanned values of a demodulated digital input signal are stored in series, a d.c. voltage quota determining circuit, which is connected to the delay line in order to calculate a d.c. voltage quota of the input signal as an average value of a selected number of the scanned values comprising:

a decoding circuit connected to the delay line and the d.c. voltage quota determining circuit which compares a multiplicity of the scanned values with the d.c. voltage quota in order to allocate a bit value to each scanned value and in this way to form a k-bit word corresponding to the input signal;

a comparison and correlation calculating circuit which compares the k-bit word corresponding to the input signal with an expected k-bit synchronization word and calculates a correlation value for the k-bit word corresponding to the input signal; and

a correlation value comparison circuit which compares the correlation value supplied by the comparison and correlation calculating circuit with a correlation threshold value in order to supply a packet identification signal if the correlation value is greater than or equal to the correlation threshold value; and

wherein

the decoding circuit comprises a multiplicity k of comparison circuits, to which in each case is applied the d.c. voltage quota and each of which is connected to one of the storage places of the delay line in order to compare the respective scanned value with the d.c. voltage quota and to determine a bit value, so the k-bit word corresponding to the input signal is applied to outputs of the decoding circuit.

10. The device according to claim 9, wherein the number of storage places of the delay line corresponds to the number k of bits in the k-bit synchronization word multiplied by an over-scanning rate, in other words with the number of scanned values per symbol.

16. The device according to claim 10, wherein the decoding circuit comprises a multiplicity k of comparison circuits, to which in each case is applied the d.c. voltage quota and each of which is connected to one of the storage places of the delay line in order to compare the respective scanned value with the d.c. voltage quota and to determine a bit value, so a k-bit word corresponding to the input signal is applied to outputs of the decoding circuit.

17. The device according to claim 10, wherein the d.c. voltage quota determining circuit has at least one addition circuit and one division circuit connected to the output of the addition circuit via a holding element, wherein one input of the addition circuit is connected to a first storage place of the delay line and another input is connected to a second storage place of the delay line which is separated from the first storage place by a multiplicity of storage places;

and

the input which is connected to the second storage place is negated and the output of the addition circuit is fed back to a third input via the holding element, so that with each addition the result of the preceding addition is added on and wherein the sum supplied by the holding circuit is divided in the division circuit by a value corresponding to the distance between the storage places in order to calculate the d.c. voltage quota.

18. The device according to claim 9, wherein the d.c. voltage quota determining circuit has at least one addition circuit and one division circuit connected to the output of the addition circuit via a holding element, wherein one input of the addition circuit is connected to a first storage place of the delay line and another input is connected to a second storage place of the delay line which is separated from the first storage place by a multiplicity of storage places;

and

the input which is connected to the second storage place is negated and the output of the addition circuit is fed back to a third input via the holding element, so that with each addition the result of the preceding addition is added on and wherein a sum supplied by the holding circuit is divided in the division circuit by a value corresponding to the distance between the storage places in order to calculate the d.c. voltage quota.

20. The method according to claim 9, wherein the number of scanned values for calculating the d.c. voltage quota includes two groups of scanned values, which are separated from one another by a multiplicity of scanned values.

11. A device for identifying data packets in a data receiving stream with a delay line which has a number of storage places, in which scanned values of a demodulated digital input signal are stored in series, and a d.c. voltage quota determining circuit, which is connected to the delay line in order to calculate a d.c. voltage quota of the input signal as an average value of a selected number of the scanned values comprising:

a decoding circuit connected to the delay line and the d.c. voltage quota determining circuit which compares a multiplicity of the scanned values with the d.c. voltage quota in order to allocate a bit value to each scanned value and to form a k-bit word corresponding to the input signal;

a comparison and correlation calculating circuit which compares the k-bit word corresponding to the input signal with an expected k-bit synchronization word and calculates a correlation value for the k-bit word corresponding to the input signal; and

a correlation value comparison circuit which compares the correlation value supplied by the comparison and correlation calculating circuit with a correlation threshold value in order to supply a packet identification signal if the correlation value is greater than or equal to the correlation threshold value; and

wherein

the d.c. voltage quota determining circuit has at least one addition circuit and one division circuit connected to the output of the addition circuit via a holding element;

one input of the addition circuit is connected to a first storage place of the delay line and another input is connected to a second storage place of the delay line, which is separated from the first storage place by a multiplicity of storage places; and

the input, which is connected to the second storage place, is negated and the output of the addition circuit is fed back to a third input via the holding element, so that with each addition the result of the preceding addition is added on and wherein a sum supplied by the holding circuit is divided in the division circuit by a value corresponding to the distance between the storage places in order to calculate the d.c. voltage quota.

12. The device according to claim 11, wherein two addition circuits connected to storage places of the delay line are provided, output signals of which are supplied to the division circuit via a further addition circuit.

13. The device according to claim 12, wherein the comparison and correlation calculating circuit operatively connected to the decoding circuit, a register storing the expected k-bit synchronization word, and a multiplicity k of comparison circuits for comparing the k-bit word with the expected k-bit synchronization word, has a correlation element which adds a one for each coinciding bit pair in order to calculate the correlation value.