Noise checking method and apparatus and computer-readable recording medium which records a noise checking program
First Claim
1. A noise checking method for performing, after carrying out cell arrangement and inter cell wiring in an integrated circuit, static noise checking on a result of the cell arrangement and the inter-cell wiring, said method comprising:
- a timing analyzing step, in which a timing chart of signal transfer on each wire is obtained by performing delay simulation with timing analysis based on the result of the cell arrangement and the inter-cell wiring;
a noise value calculating step, in which a noise value is calculated, said noise value representing a degree at which at least one affecting wire (hereinafter will be called the “
aggressor”
), running in parallel with an object wire (hereinafter will be called the “
victim”
) to be checked, induces noise onto the victim;
a noise value evaluating step, in which it is evaluated whether or not the noise value calculated at said noise value calculating step exceeds a limit value; and
an error evaluating step, in which, if it is evaluated at said noise value evaluating step that the noise value is greater than the limit value, comparison is performed, based on the timing chart obtained at said timing analyzing step, between a last edge appearance timing in a signal waveform transmitted on the victim and a last edge appearance timing in a signal waveform transmitted on the aggressor, and then a decision is made on a noise value error in the victim based on the comparison result.
1 Assignment
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Accused Products
Abstract
The apparatus reduces the amount of correction for noise value error, so as to reduce work needed for correction to ensure error avoidance, and to improve the freedom of layout design, and to reduce load on DA. Based on a timing chart of signal transfer on each wire, the last edge appearance timing in the signal waveform of a victim whose noise value exceeds a limit value is compared with the last edge appearance timing in the signal waveform of an aggressor, to evaluate the noise value error in the victim. The apparatus is used in static noise checking of cell arrangement and inter-cell wiring after such cell arrangement and inter-cell wiring are performed at design of integrated circuits such as LSIs.
160 Citations
24 Claims
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1. A noise checking method for performing, after carrying out cell arrangement and inter cell wiring in an integrated circuit, static noise checking on a result of the cell arrangement and the inter-cell wiring, said method comprising:
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a timing analyzing step, in which a timing chart of signal transfer on each wire is obtained by performing delay simulation with timing analysis based on the result of the cell arrangement and the inter-cell wiring; a noise value calculating step, in which a noise value is calculated, said noise value representing a degree at which at least one affecting wire (hereinafter will be called the “
aggressor”
), running in parallel with an object wire (hereinafter will be called the “
victim”
) to be checked, induces noise onto the victim;a noise value evaluating step, in which it is evaluated whether or not the noise value calculated at said noise value calculating step exceeds a limit value; and an error evaluating step, in which, if it is evaluated at said noise value evaluating step that the noise value is greater than the limit value, comparison is performed, based on the timing chart obtained at said timing analyzing step, between a last edge appearance timing in a signal waveform transmitted on the victim and a last edge appearance timing in a signal waveform transmitted on the aggressor, and then a decision is made on a noise value error in the victim based on the comparison result. - View Dependent Claims (5, 7)
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2. A noise checking method for performing, after carrying out cell arrangement and inter cell wiring in an integrated circuit, a static noise checking on a result of the cell arrangement and the inter-cell wiring, said method comprising:
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a timing analyzing step, in which a timing chart of signal transfer on each wire is obtained by performing delay simulation with timing analysis based on the result of the cell arrangement and the inter-cell wiring; a one-to-one noise value calculating step, in which a one-to-one noise value is calculated, said one-to-one noise value representing a degree at which one affecting wire (hereinafter will be called the “
aggressor”
), running in parallel with an object wire (hereinafter will be called the “
victim”
) to be checked, induces noise onto the victim;a one-to-one noise value evaluating step, in which it is evaluated whether or not the one-to-one noise value, calculated at said one-to-one noise value calculating step, exceeds a first limit value; a one-to-n noise value calculating step, in which, if it is evaluated at said one-to-one noise value evaluating step that the one-to-one noise value does not exceed the first limit value, a one-to-n noise value is calculated, said one-to-n noise value representing a degree at which n (n is a natural number equal to or greater than
2) aggressors, running in parallel with the victim, induces noise onto the victim;a one-to-n noise value evaluating step, in which it is evaluated whether or not the one-to-n noise value, calculated at said one-to-n noise value calculating step, exceeds a second limit value; and a first error evaluating step, in which, if it is evaluated at said one-to-n noise value evaluating step that the one-to-n noise value exceeds the second limit value, comparison is performed, based on the timing chart obtained at said timing analyzing step, between a last edge appearance timing in a signal waveform transmitted on the victim and last edge appearance timings in signal waveforms transmitted on the n aggressors, and then a decision is made on a noise value error in the victim based on the comparison result. - View Dependent Claims (3, 4, 6, 8)
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9. A noise checking apparatus for performing, after carrying out cell arrangement and inter cell wiring in an integrated circuit, static noise checking on a result of the cell arrangement and the inter-cell wiring, said apparatus comprising:
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a timing analyzing unit, in which a timing chart of signal transfer on each wire is obtained by performing delay simulation with timing analysis based on the result of the cell arrangement and the inter-cell wiring; a noise value calculating unit, in which a noise value is calculated, said noise value representing a degree at which at least one affecting wire (hereinafter will be called the “
aggressor”
), running in parallel with an object wire (hereinafter will be called the “
victim”
) to be checked, induces noise onto the victim;a noise value evaluating unit, in which it is evaluated whether or not the noise value calculated by said noise value calculating unit exceeds a limit value; and an error evaluating unit, in which, if it is evaluated by said noise value evaluating unit that the noise value is greater than the limit value, comparison is performed, based on the timing chart obtained by said timing analyzing unit, between a last edge appearance timing in a signal waveform transmitted on the victim and a last edge appearance timing in a signal waveform transmitted on the aggressor, and then a decision is made on a noise value error in the victim based on the comparison result. - View Dependent Claims (13, 15)
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10. A noise checking apparatus for performing, after carrying out cell arrangement and inter cell wiring in an integrated circuit, static noise checking on a result of the cell arrangement and the inter-cell wiring, said apparatus comprising:
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a timing analyzing unit, in which a timing chart of signal transfer on each wire is obtained by performing delay simulation with timing analysis based on the result of the cell arrangement and the inter-cell wiring; a one-to-one noise value calculating unit, in which a one-to-one noise value is calculated, said one-to-one noise value representing a degree at which one affecting wire (hereinafter will be called the “
aggressor”
), running in parallel with an object wire (hereinafter will be called the “
victim”
) to be checked, induces noise onto the victim;a one-to-one noise value evaluating unit, in which it is evaluated whether or not the one-to-one noise value, calculated by said one-to-one noise value calculating unit, exceeds a first limit value; a one-to-n noise value calculating unit, in which, if it is evaluated by said one-to-one noise value evaluating unit that the one-to-one noise value does not exceed the first limit value, a one-to-n noise value is calculated, said one-to-n noise value representing a degree at which n (n is a natural number equal to or greater than
2) aggressors, running in parallel with the victim, induces noise onto the victim;a one-to-n noise value evaluating unit, in which it is evaluated whether or not the one-to-n noise value, calculated by said one-to-n noise value calculating unit, exceeds a second limit value; and a first error evaluating unit, in which, if it is evaluated by said one-to-n noise value evaluating unit that the one-to-n noise value exceeds the second limit value, comparison is performed, based on the timing chart obtained by said timing analyzing unit, between a last edge appearance timing in a signal waveform transmitted on the victim and last edge appearance timings in signal waveforms transmitted on the n aggressors, and then a decision is made on a noise value error in the victim based on the comparison result. - View Dependent Claims (11, 12, 14, 16)
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17. A computer-readable recording medium in which is recorded a noise checking program for a computer to function as a noise checking apparatus for performing, after carrying out cell arrangement and inter cell wiring in an integrated circuit, static noise checking on a result of the cell arrangement and the inter-cell wiring, said program instructing the computer to function as the following:
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a timing analyzing unit, in which a timing chart of signal transfer on each wire is obtained by performing delay simulation with timing analysis based on the result of the cell arrangement and the inter-cell wiring; a noise value calculating unit, in which a noise value is calculated, said noise value representing a degree at which at least one affecting wire (hereinafter will be called the “
aggressor”
), running in parallel with an object wire (hereinafter will be called the “
victim”
) to be checked, induces noise onto the victim;a noise value evaluating unit, in which it is evaluated whether or not the noise value calculated by said noise value calculating unit exceeds a limit value; and an error evaluating unit, in which, if it is evaluated at said noise value evaluating step that the noise value is greater than the limit value, comparison is performed, based on the timing chart obtained by said timing analyzing unit between a last edge appearance timing in a signal waveform transmitted on the victim and a last edge appearance timing in a signal waveform transmitted on the aggressor, and then a decision is made on a noise value error in the victim based on the comparison result. - View Dependent Claims (21, 23)
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18. A computer-readable recording medium in which is recorded a noise checking program for a computer to function as a noise checking apparatus for performing, after carrying out cell arrangement and inter cell wiring in an integrated circuit, static noise checking on a result of the cell arrangement and the inter-cell wiring, said program instructing the computer to function as the following:
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a timing analyzing unit, in which a timing chart of signal transfer on each wire is obtained by performing delay simulation with timing analysis based on the result of the cell arrangement and the inter-cell wiring; a one-to-one noise value calculating unit, in which a one-to-one noise value is calculated, said one-to-one noise value representing a degree at which one affecting wire (hereinafter will be called the “
aggressor”
), running in parallel with an object wire (hereinafter will be called the “
victim”
) to be checked, induces noise onto the victim;a one-to-one noise value evaluating unit, in which it is evaluated whether or not the one-to-one noise value, calculated by said one-to-one noise value calculating unit, exceeds a first limit value; a one-to-n noise value calculating unit, in which, if it is evaluated by said one-to-one noise value evaluating unit that the one-to-one noise value does not exceed the first limit value, a one-to-n noise value is calculated, said one-to-n noise value representing a degree at which n (n is a natural number equal to or greater than
2) aggressors, running in parallel with the victim, induces noise onto the victim;a one-to-n noise value evaluating unit, in which it is evaluated whether or not the one-to-n noise value, calculated by said one-to-n noise value calculating unit, exceeds a second limit value; and a first error evaluating unit, in which, if it is evaluated by said one-to-n noise value evaluating unit that the one-to-n noise value exceeds the second limit value, comparison is performed, based on the timing chart obtained by said timing analysis unit, between a last edge appearance timing in a signal waveform transmitted on the victim and last edge appearance timings in signal waveforms transmitted on the n aggressors, and then a decision is made on a noise value error in the victim based on the comparison result. - View Dependent Claims (19, 20, 22, 24)
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Specification