Streaming vector processor with reconfigurable interconnection switch

• US 7,159,099 B2
• Filed: 06/28/2002
• Issued: 01/02/2007
• Est. Priority Date: 06/28/2002
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Essick, Raymond B. IV, Chiricescu, Silviu, May, Philip E., Norris, James M., Lucas, Brian Geoffrey, Saidi, Ali, Schuette, Michael Allen, Moat, Kent Donald
• Primary Examiner(s): Fleming; Fritz
• Assistant Examiner(s): DOLLINGER, TONIA LYNN MEONSKE
• Application Number:
  US10/184,583
• Publication Number:
  US 20040003206A1
• Time in Patent Office: 1,649 Days
• Field of Search: 712/218, 712 2- 9, 712/15, 712/37, 712/43, 712/245, 712/229, 717/144
• US Class Current: 712/218
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/8061 Details on data memory access
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3455 using stride
• CPC Class Codes: G06F 9/3552 using wraparound, e.g. modulo or circular addressing
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A re-configurable, streaming vector processor (100) is provided which includes a number of function units (102), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch (104) and a micro-sequencer (118). The re-configurable interconnection switch (104) includes one or more links, each link operable to couple an output of a function unit (102) to an input of a function unit (102) as directed by the micro-sequencer (118). The vector processor may also include one or more input-stream units (122) for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface (116) to the host processor. The vector processor also includes one or more output-stream units (124) for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model. The instructions stored in a memory, in the sequence that direct the re-configurable interconnection switch, form a second part of the programming model.

Claims

1. A re-configurable, streaming vector processor comprising:

a plurality of function units, each comprising one of a shifter, an adder;

a logic unit and a multiplier and having one or more inputs for receiving

a data value and an output for storing a data value;

a re-configurable interconnection switch comprising a plurality of links, each link comprising an input switch operable to select between the outputs of at least two of the plurality of function units and an output switch operable to select between the inputs of at least two of the plurality of function units and each link operable to form a datapath between an output of a function unit and an input of the one or more inputs of a function unit; and

a micro-sequencer coupled to the re-configurable interconnection switch and operable to control the re-configurable interconnection switch,

wherein the micro-sequencer is operable to produce one or more control words that cause a data value stored at the output of a function unit to traverse, in a single cycle of a processor clock, the datapath formed by a link of the plurality of links.

2. A re-configurable, streaming vector processor in accordance with claim 1, wherein the mico-sequencer includes a program memory for storing a program of instructions.

3. A re-configurable, streaming vector processor in accordance with claim 1, wherein the re-configurable interconnection switch includes a switch memory for storing data values.

4. A re-configurable, streaming vector processor in accordance with claim 3, wherein the switch memory comprises at least one of a FIFO, a programmed delay and a plurality of registers configured to form a data pipeline.

5. A re-configurable, streaming vector processor in accordance with claim 1, wherein a link of the re-configurable interconnection switch is directed by the micro-sequencer to receive a data value from an output of a function unit and to provide a data value to an input of the one or more inputs of a function unit.

6. A re-configurable, streaming vector processor in accordance with claim 1, further comprising:

one or more input stream units coupled to the re-configurable interconnection switch and operable, in response to a single control instruction, to retrieve a plurality of input data values from a data memory and to provide the plurality of input data values to the re-configurable interconnection switch; and

one or more output stream units coupled to the output of the re-configurable interconnection switch and operable to receive data values from the re-configurable interconnection switch and to provide output data values to a data memory.

7. A re-configutable, streaming vector processor in accordance with claim 6, wherein the input and output stream units include an interface for receiving control instructions from a host computer.

8. A re-configurable, streaming vector processor in accordance with claim 7, wherein the control instructions comprises at least one of:

a starting address of a vector of data values in the data memory;

a span of the vector of data values;

a stride between data values;

a number of memory addresses to skip between a span of vector data values; and

a size of each data value in the vector of data values.

9. A re-configurable, streaming vector processor in accordance with claim 6, further comprising an external interface operable to couple to the input stream units, the output stream units and the micro-sequencer to a host computer.

10. A re-configurable, streaming vector processor in accordance with claim 1, wherein the function units further comprise a passthrough function unit.

11. A re-configurable, streaming vector processor in accordance with claim 1, wherein an output of at least one of the plurality of function units comprises a pipeline of registers.

12. A re-configurable, streaming vector processor in accordance with claim 1, further comprising at least one accumulator coupled to the re-configurable interconnection switch.

13. A re-configurable, streaming vector processor in accordance with claim 12, wherein the at least one accumulator is operable to be coupled to a host computer.

14. A re-configurable, streaming vector processor in accordance with claim 1, further comprising a plurality of scaler registers.

15. A re-configurable, streaming vector processor in accordance with claim 14, wherein the plurality of scaler registers provide a data tunnel.

16. A method for operating a streaming vector processor comprising an interconnection switch having a plurality of links, a micro-sequencer and a plurality of function units each having an output and one or more inputs, the method comprising:

storing a program of instructions in the micro-sequencer;

in a single instruction cycle of the streaming vector processor;

retrieving an instruction of the program of instructions;

configuring the interconnection switch in accordance with the instruction retrieved from the program of instructions to provide a datapath between the output of a first function unit of the plurality of function units and an input of the one or more inputs of a second function unit of the plurality of function units;

moving a first data value stored at the output the first function unit to the input of the second function unit along the datapath;

the second function unit operating on the first data value to produce a second data value; and

storing the second data value at the output of the second function unit,

wherein configuring the interconnection switch in accordance with the instruction retrieved from the program of instructions comprises;

configuring an input switch of a link of the plurality of links to select the output of the first function unit; and

configuring an output switch of the link to select an input of the second function unit.

17. A method in accordance with claim 16, wherein the streaming vector processor further comprises one or more input stream units having a buffer memory and wherein the method further comprises:

configuring the interconnection switch in accordance the instruction retrieved from the program of instructions to provide a direct datapath along a link of the interconnection switch between an input stream unit of the one or more input stream units and an input of the one or more inputs of a second function unit of the plurality of function units.

18. A method in accordance with claim 17, the method further comprising each input stream unit retrieving data values from an external memory and storing them in the buffer memory of the input stream unit in accordance with a set parameters received from a host processor.

19. A method in accordance with claim 16, wherein the streaming vector processor further comprises one or more output stream units having a buffer memory and wherein the method further comprises:

configuring the interconnection switch in accordance the instruction retrieved from the program of instructions to provide a direct datapath along a link of the interconnection switch between the output of a first function unit of the plurality of function units and an output stream unit of the one or more output stream units.

20. A method in accordance with claim 19, further comprising each output stream unit writing data values from the buffer memory of the output stream unit to an external memory in accordance with a set parameters received from a host processor.