Semiconductor integrated circuit with security function

• US 7,159,153 B2
• Filed: 02/03/2003
• Issued: 01/02/2007
• Est. Priority Date: 02/05/2002
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jong-Cheol
• Primary Examiner(s): Baderman; Scott
• Assistant Examiner(s): LOHN, JOSHUA A
• Application Number:
  US10/357,146
• Publication Number:
  US 20030149914A1
• Time in Patent Office: 1,429 Days
• Field of Search: 714/47, 714/48, 714/49
• US Class Current: 714/48
• CPC Class Codes: G06F 21/87 by means of encapsulation, e.g. for integrated circuits
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14

Abstract

An IC (integrated circuit) card (or smart card) comprising a plurality of detectors for detecting abnormal operating conditions of the IC card. If an abnormal condition is detected by one of the detectors, the detector will generate a detection signal, which is then stored in a nonvolatile memory. A reset signal is then generated in response to the detection signal to reset a central processor unit. The central processor unit informs a user of a reset status and a cause thereof.

Claims

1. A semiconductor integrated circuit, comprising:

a plurality of detectors, wherein each detector detects a corresponding operating condition of the integrated circuit and generates a detection signal that indicates an abnormal condition;

a reset signal generator for generating a reset signal;

a nonvolatile memory;

a plurality of latch circuits for respectively latching the detection signals from the plurality of detectors, output signals from said plurality of latch circuits being fed to the nonvolatile memory;

a logic circuit connected to said output signals from said plurality of latch circuits and producing a program signal upon a latch output signal indicating an abnormal condition, said program signal fed to said nonvolatile memory to cause said latch circuit outputs to be stored therein and said program signal being fed to said reset signal generator for generating a reset signal in response thereto; and

a central processor unit (CPU) which is restarted in response to the reset signal after the detection signals have been stored in the nonvolatile memory in response to the program signal from the logic circuit, wherein upon restarting the CPU, a read signal is generated by the CPU to automatically read out stored detection signals from the nonvolatile memory to be referred to by a user to indicate there was an abnormal condition detected.

2. The integrated circuit of claim 1, further comprising a timer that generates a timer control signal fed to the reset signal generator when a predetermined time has elapsed after the program signal is produced by the logic circuit.

3. The integrated circuit of claim 2, wherein the reset signal generator generates the reset signal in response to the timer control signal.

4. The integrated circuit of claim 2, wherein the predetermined time is substantially equal to a time needed for writing the detection signals into the nonvolatile memory in response to the program signal.

5. The integrated circuit of claim 1, wherein the nonvolatile memory comprises a plurality of memory cells for storing the detection signals.

6. The integrated circuit of claim 5, wherein the memory cells comprise electrically erasable and programmable read-only memory cells.

7. The integrated circuit of claim 1, wherein the detectors comprise a frequency detector for sensing a frequency of a system clock, a voltage detector for sensing a power supply voltage, a temperature detector for sensing temperature, or light detector for sensing light exposure, or any combination thereof.

8. An IC (integrated circuit) card, comprising:

an embedded CPU (central processing unit);

a plurality of detectors, wherein each detector detects a corresponding operating condition of the IC card and generates a detection signal that indicates an abnormal condition;

a reset signal generator for generating a reset signal;

a nonvolatile memory;

a plurality of latch circuits for respectively latching the detection signals from the plurality of detectors, output signals from said plurality of latches being fed to the nonvolatile memory; and

a logic circuit connected to said output signals from said plurality of latch circuits and producing a program signal upon a latch output signal indicating an abnormal condition, said program signal fed to said nonvolatile memory to cause said latch circuit outputs to be stored therein and said program signal being fed to said reset signal generator for generating a reset signal in response thereto,

wherein the embedded CPU is restarted in response to the reset signal after the detection signals have been stored in the nonvolatile memory in response to the program signal from the logic circuit, and wherein upon resetting of the CPU, a read signal is generated by the CPU to automatically read out a stored detection signal from the nonvolatile memory to be referred to by a user to indicate there was an abnormal condition detected.

9. The IC card of claim 8, further comprising a timer that generates a timer control signal fed to the reset generator when a predetermined time has elapsed after the program signal is produced by the logic circuit.

10. The IC card of claim 9, wherein the predetermined time is substantially equal to a time needed for writing the detection signals into the nonvolatile memory in response to the program signal.

11. The IC card of claim 8, wherein the nonvolatile memory comprises a plurality of memory cells for storing the detection signals.

12. The IC card of claim 11, wherein the memory cells comprise electrically erasable and programmable read-only memory cells.

13. The IC card of claim 8, wherein the detectors comprise a frequency detector for sensing a frequency of a system clock, a voltage detector for sensing a power supply voltage, a temperature detector for sensing temperature, or a light detector for sensing light exposure, or any combination thereof.

14. A method for monitoring operation of an integrated circuit, comprising the steps of:

detecting a plurality of operating conditions of an integrated circuit;

generating a detection signal if an abnormal operating condition is detected;

storing the detection signal in nonvolatile memory;

generating a reset signal;

latching the detection signals from the step of generating feeding latched output signals to said nonvolatile memory;

producing a program signal upon a latched output signal indicating an abnormal condition, feeding said program signal to said nonvolatile memory to cause said latched outputs to be stored therein and said program signal being used to start said step of generating a reset signal;

resetting a CPU (central processing unit) in response to the reset signal after the detection signal has been stored in the nonvolatile memory; and

automatically reading out the stored detection signal from the nonvolatile memory after resetting the CPU in response to a read signal generated by the CPU upon resetting of the CPU.

15. The method of claim 14, wherein the predetermined time is substantially equal to a time needed for storing the detection signal in response to the program signal.

16. The method of claim 14, wherein the step of detecting comprises detecting a frequency of a system clock, detecting a power supply voltage, detecting temperature, or detecting light exposure, or any combination thereof.