Vertically stacked field programmable nonvolatile memory and method of fabrication

• US 7,160,761 B2
• Filed: 09/19/2002
• Issued: 01/09/2007
• Est. Priority Date: 11/16/1998
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Cleeves, James M., Subramanian, Vivek
• Primary Examiner(s): Vu; David
• Application Number:
  US10/251,206
• Publication Number:
  US 20030016553A1
• Time in Patent Office: 1,573 Days
• Field of Search: 428128-132, 428/197, 428/210, 428600-601, 428/467, 257/50, 257/530, 257/E23.147, 257/E23.149
• US Class Current: 438/131
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Claims

1. A process for fabricating a memory cell comprising:

forming a steering element that includes a polycrystalline semiconductor layer of a first conductivity type; and

forming a state change element adjacent to the steering element,

wherein the state change element includes a dielectric rupture layer, and

wherein the dielectric rupture layer is formed by plasma oxidation of the semiconductor layer, wherein the step of forming a steering element comprises forming a steering element containing metal elements, and wherein the plasma oxidation process is carried out at a temperature below that at which the metal elements can interdiffuse in the steering element, wherein the steering element comprises a Schottky diode.

2. The process of claim 1, wherein the plasma oxidation process comprises a process carried out at no more than about 400°

C.

3. The process of claim 1, wherein the step of forming a steering element containing metal elements comprises forming a refractory metal.

4. The process of claim 1, wherein the step of forming a steering element containing metal elements comprises forming a refractory metal silicide.

5. A process for fabricating a memory cell comprising:

providing an electrically active element in a steering element of the memory cell; and

oxidizing the electrically active element in a plasma oxidation process to form an oxide antifuse, wherein providing an electrically active element comprises forming one of an active component of P/N junction or an active component of a Schottky diode.

6. A process for fabricating a memory cell comprising:

forming a P/N junction having an n-type component and a p-type component; and

plasma oxidizing one of the n-type component or the p-type component to form an oxide antifuse.

7. The process of claim 6, wherein fonmng a P/N junction comprises:

forming a first semiconductor layer of a first conductivity type; and

forming a second semiconductor layer of a second conductivity type overlying and in intimate contact with the first semiconductor layer.

8. The process of claim 7 further comprising forming a third scniiconductor layer having a conductivity-determining dopant overlying and in intimate contact with the oxide antifuse.

9. The process of claim 8, wherein the plasma oxidation process oxidizes the second semiconductor layer, and wherein forming a third semiconductor layer comprises forming a semiconductor layer of the second conductivity type.

10. The process of claim 6, wherein forming a P/N junction comprises forming the p-type component overlying and in intimate contact with a conductor layer of the memory cell.

11. A process for fabricating a memory cell comprising:

forming a conductor layer;

forming a first semiconductor layer having a first conductivity type overlying and in intimate contact with the conductor layer;

forming a second semiconductor layer having a second conductivity type overlying and in intimate contact with the first semiconductor layer;

plasma oxidizing the second semiconductor layer to form an oxide antifuse; and

forming a third semiconductor layer having the second conductivity type overlying and in intimate contact with the oxide antifuse.

12. The process of claim 11, wherein forming a first semiconductor layer having a first conductivity type comprises forming a semiconductor layer having a p-type conductivity, and wherein forming a second semiconductor layer having a second conductivity type comprises forming a semiconductor layer having an n-type conductivity.

13. The process of claim 11, wherein forming a conductor layer comprises forming a refractory metal lead that electrically connects the memory cell with an adjacent memory cell.

14. The process of claim 13, wherein forming a refractory metal lead comprises forming a lead of molybdenum or tungsten.

15. The process of claim 13, wherein plasma oxidizing comprises a process carried out at no more than about 400°

C.